Solid state imaging device and electronic apparatus

ABSTRACT

The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area. The present technology can be applied to, for example, a solid state imaging device such as a CMOS image sensor.

TECHNICAL FIELD

The present technology relates to a solid state imaging device and anelectronic apparatus, and particularly relates to a solid state imagingdevice with a stacked structure, and an electronic apparatus includingthe solid state imaging device with the stacked structure.

BACKGROUND ART

When a solid state imaging device with a larger area than the exposurefield of an exposure apparatus is manufactured, split exposure hasconventionally been used which splits the solid state imaging deviceinto a plurality of areas and exposes each split area (see, for example,Patent Document 1).

Moreover, in order to improve the aperture ratio of a solid stateimaging device, a stacking technology has conventionally been used whichforms a pixel circuit including a pixel array unit and a signalprocessing circuit respectively in different semiconductor substrates,stacks the two semiconductor substrates, and connects them electrically(see, for example, Patent Document 2).

In addition, if, for example, a solid state imaging device with thestacked structure having an area larger than the exposure field of anexposure apparatus is manufactured, split exposure is performed on eachsemiconductor substrate.

Moreover, a technology has conventionally been proposed which preventsmoisture from entering a multi-core semiconductor device that can beseparated into small units, through a mutually connected wire connectingbetween the cores when detached into the small units (see, for example,Patent Document 3).

CITATION LIST Patent Document

-   Patent Document 1: Japanese Patent No. 2902506-   Patent Document 2: Japanese Patent No. 4497844-   Patent Document 3: Japanese Patent Application Laid-Open No.    2013-21131

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

However, split exposure requires the use of a photomask differentaccording to each split area and highly accurate positioning at aconnection portion of the split areas; therefore, the manufacturingprocess becomes complicated and also the manufacturing cost increases.

On the other hand, even if an attempt is made to reduce themanufacturing cost, it is required to ensure moisture resistance andprevent a reduction in the reliability of a solid state imaging deviceas in the invention described in Patent Document 3.

Hence, the present technology is to enable a reduction in manufacturingcost without reducing the reliability of a solid state imaging device.

Solutions to Problems

A solid state imaging device of a first aspect of the present technologyincludes: a first substrate including a pixel circuit having a pixelarray unit; and a second substrate including a first and a second signalprocessing circuit arranged side by side across a scribe area, whereinthe first substrate and the second substrate are stacked, and the secondsubstrate includes a first moisture-resistant ring surrounding at leastpart of a periphery of the first signal processing circuit, a secondmoisture-resistant ring surrounding at least part of a periphery of thesecond signal processing circuit, a third moisture-resistant ringsurrounding at least part of a periphery of the second substrate in alayer different from the first and second moisture-resistant rings, anda barrier unit separating a first area between the first and secondmoisture-resistant rings and a second area, at least part of a peripheryof which is surrounded by the third moisture-resistant ring, and havingmoisture resistance.

The barrier unit may include a dummy wire being a wire that is not usedto transmit a signal.

The barrier unit may include a plurality of the dummy wires formed in aplurality of wiring layers, and a via connecting the dummy wires indifferent wiring layers.

The dummy wires in a first wiring layer and the dummy wires in a secondwiring layer adjacent to the first wiring layer can be alternatelyplaced in a first direction in which the scribe area extends, or asecond direction perpendicular to the first direction in at least partof the barrier unit.

A wire that connects the first and second signal processing circuits canbe formed in the first or second wiring layer that is closer to thethird moisture-resistant ring.

The second substrate is further provided with a fourthmoisture-resistant ring formed, leaving a predetermined space from thefirst and second moisture-resistant rings, in such a manner as tosurround at least part of a periphery of the scribe area, and it ispossible to cause the barrier unit to separate a third area between thefirst and fourth moisture-resistant rings and the second area, and afourth area between the second and fourth moisture-resistant rings andthe second area, between the first area and the second area.

It is possible to form at least part of a layer including the first andsecond moisture-resistant rings by one-shot exposure, and form layersincluding the third moisture-resistant ring and the barrier unit bysplit exposure.

An inter-layer insulating film between the layer including the barrierunit and an adjacent layer thereof may include a low-K film.

A wire that connects the first and second signal processing circuits canbe formed in the layer including the third moisture-resistant ring.

It is possible to form the pixel circuit by split exposure, and form atleast part of the layers of the signal processing circuits by one-shotexposure.

An electronic apparatus of a second aspect of the present technologyincludes a solid state imaging device including a first substrateincluding a pixel circuit having a pixel array unit, and a secondsubstrate including a first and a second signal processing circuitarranged side by side across a scribe area, wherein the first substrateand the second substrate are stacked, and the second substrate includesa first moisture-resistant ring surrounding at least part of a peripheryof the first signal processing circuit, a second moisture-resistant ringsurrounding at least part of a periphery of the second signal processingcircuit, a third moisture-resistant ring surrounding at least part of aperiphery of the second substrate in a layer different from the firstand second moisture-resistant rings, and a barrier unit separating afirst area between the first and second moisture-resistant rings and asecond area, at least part of a periphery of which is surrounded by thethird moisture-resistant ring, and having moisture resistance.

In the first and second aspects of the present technology, moisture isprevented from entering the second area, at least part of the peripheryof which is surrounded by the third moisture-resistant ring, from thefirst area between the first and second moisture-resistant rings.

Effects of the Invention

According to the first or second aspect of the present technology, themanufacturing cost can be reduced without reducing the reliability of asolid state imaging device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a perspective view schematically illustrating a solid stateimaging device according to a first embodiment of the presenttechnology.

FIG. 2 is a circuit diagram illustrating specific configurations of apixel circuit and signal processing circuits of the solid state imagingdevice according to the first embodiment.

FIG. 3 is a block diagram illustrating a specific configuration exampleof a signal processing unit of the solid state imaging device accordingto the first embodiment.

FIG. 4 is a diagram schematically illustrating the layout of a logicsubstrate of the solid state imaging device according to the firstembodiment.

FIG. 5 is a diagram illustrating an example of a method for connectingthe signal processing circuits.

FIG. 6 is a diagram for describing an imaging process of the solid stateimaging device according to the first embodiment.

FIG. 7 is a diagram for describing setting methods for the left andright signal processing circuits.

FIG. 8 is a diagram for describing the setting methods for the left andright signal processing circuits.

FIG. 9 is a diagram for describing a method for manufacturing the solidstate imaging device according to the first embodiment.

FIG. 10 is a diagram for describing the method for manufacturing thesolid state imaging device according to the first embodiment.

FIG. 11 is a diagram for describing the method for manufacturing thesolid state imaging device according to the first embodiment.

FIG. 12 is a diagram for describing the method for manufacturing thesolid state imaging device according to the first embodiment.

FIG. 13 is a diagram for describing the method for manufacturing thesolid state imaging device according to the first embodiment.

FIG. 14 is a perspective view schematically illustrating a solid stateimaging device according to a second embodiment of the presenttechnology.

FIG. 15 is a diagram for describing an imaging process of the solidstate imaging device according to the second embodiment.

FIG. 16 is a diagram for describing a method for manufacturing the solidstate imaging device according to the second embodiment.

FIG. 17 is a diagram for describing the method for manufacturing thesolid state imaging device according to the second embodiment.

FIG. 18 is a diagram for describing the method for manufacturing thesolid state imaging device according to the second embodiment.

FIG. 19 is a diagram for describing the method for manufacturing thesolid state imaging device according to the second embodiment.

FIG. 20 is a perspective view schematically illustrating a solid stateimaging device according to a third embodiment of the presenttechnology.

FIG. 21 is a cross-sectional view schematically illustrating the solidstate imaging device according to the third embodiment of the presenttechnology.

FIG. 22 is a diagram illustrating an example of a method for connectingsignal processing circuits.

FIG. 23 is a diagram schematically illustrating configuration examplesof a pixel substrate and a logic substrate of when a pixel AD conversiontechnique is adopted.

FIG. 24 is a plan view schematically illustrating a first embodiment ofthe logic substrate configured to avoid interference between a wire inan inter-circuit wiring layer and a moisture-resistant ring.

FIG. 25 is a cross-sectional view schematically illustrating a firstembodiment of the moisture-resistant ring.

FIG. 26 is a perspective view schematically illustrating the firstembodiment of the moisture-resistant ring.

FIG. 27 is a plan view schematically illustrating a second embodiment ofa logic substrate configured to avoid interference between a wire in aninter-circuit wiring layer and a moisture-resistant ring.

FIG. 28 is a first cross-sectional view schematically illustrating asecond embodiment of the moisture-resistant ring.

FIG. 29 is a first perspective view schematically illustrating thesecond embodiment of the moisture-resistant ring.

FIG. 30 is a second cross-sectional view schematically illustrating thesecond embodiment of the moisture-resistant ring.

FIG. 31 is a second perspective view schematically illustrating thesecond embodiment of the moisture-resistant ring.

FIG. 32 is a third cross-sectional view schematically illustrating thesecond embodiment of the moisture-resistant ring.

FIG. 33 is a third perspective view schematically illustrating thesecond embodiment of the moisture-resistant ring.

FIG. 34 is a diagram for describing a method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 35 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 36 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 37 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 38 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 39 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 40 is a diagram for describing the method for manufacturing thesecond embodiment of the moisture-resistant ring.

FIG. 41 is a plan view schematically illustrating a third embodiment ofthe logic substrate configured to avoid interference between a wire inan inter-circuit wiring layer and a moisture-resistant ring.

FIG. 42 is an image diagram schematically illustrating dummy wiresforming the third embodiment of the moisture-resistant ring.

FIG. 43 is a perspective view schematically illustrating the thirdembodiment of the moisture-resistant ring.

FIG. 44 is a perspective view schematically illustrating parts of layersof the third embodiment of the moisture-resistant ring.

FIG. 45 is a perspective view schematically illustrating a fourthembodiment of the moisture-resistant ring.

FIG. 46 is a perspective view schematically illustrating parts of layersof the fourth embodiment of the moisture-resistant ring.

FIG. 47 is an A-A cross-sectional view illustrating the fourthembodiment of the moisture-resistant ring.

FIG. 48 is a B-B cross-sectional view illustrating the fourth embodimentof the moisture-resistant ring.

FIG. 49 is a perspective view schematically illustrating a fifthembodiment of the moisture-resistant ring.

FIG. 50 is a perspective view schematically illustrating parts of layersof the fifth embodiment of the moisture-resistant ring.

FIG. 51 is a perspective view schematically illustrating parts of layersof the fifth embodiment of the moisture-resistant ring.

FIG. 52 is a perspective view schematically illustrating parts of layersof the fifth embodiment of the moisture-resistant ring.

FIG. 53 is an A-A cross-sectional view illustrating the fifth embodimentof the moisture-resistant ring.

FIG. 54 is a B-B cross-sectional view illustrating the fifth embodimentof the moisture-resistant ring.

FIG. 55 is a perspective view schematically illustrating a sixthembodiment of the moisture-resistant ring.

FIG. 56 is a perspective view schematically illustrating parts of layersof the sixth embodiment of the moisture-resistant ring.

FIG. 57 is a perspective view schematically illustrating parts of layersof the sixth embodiment of the moisture-resistant ring.

FIG. 58 is a perspective view schematically illustrating parts of thelayer of the sixth embodiment of the moisture-resistant ring.

FIG. 59 is an A-A cross-sectional view illustrating the sixth embodimentof the moisture-resistant ring.

FIG. 60 is a B-B cross-sectional view illustrating the sixth embodimentof the moisture-resistant ring.

FIG. 61 is a perspective view schematically illustrating a modificationof the sixth embodiment of the moisture-resistant ring.

FIG. 62 is an A-A cross-sectional view illustrating the modification ofthe sixth embodiment of the moisture-resistant ring.

FIG. 63 is a B-B cross-sectional view illustrating the modification ofthe sixth embodiment of the moisture-resistant ring.

FIG. 64 is a perspective view schematically illustrating a seventhembodiment of the moisture-resistant ring.

FIG. 65 is a perspective view schematically illustrating parts of layersof the seventh embodiment of the moisture-resistant ring.

FIG. 66 is a perspective view schematically illustrating parts of layersof the seventh embodiment of the moisture-resistant ring.

FIG. 67 is an A-A cross-sectional view illustrating the seventhembodiment of the moisture-resistant ring.

FIG. 68 is a B-B cross-sectional view illustrating the seventhembodiment of the moisture-resistant ring.

FIG. 69 is a perspective view schematically illustrating the seventhembodiment of the moisture-resistant ring.

FIG. 70 is an A-A cross-sectional view illustrating an eighth embodimentof the moisture-resistant ring.

FIG. 71 is a B-B cross-sectional view illustrating the eighth embodimentof the moisture-resistant ring.

FIG. 72 is a block diagram illustrating a configuration example of anelectronic apparatus.

MODES FOR CARRYING OUT THE INVENTION

Modes for carrying out the present technology (hereinafter referred toas the embodiments) are described hereinafter. Incidentally,descriptions are given in the following order:

1. First embodiment (an example where signal processing circuits are notelectrically connected)2. Second embodiment (an example where the signal processing circuitsare electrically connected in a logic substrate)3. Third embodiment (an example where the signal processing circuits areelectrically connected in a pixel substrate)

4. Modifications 1. First Embodiment {1-1. System Configuration}

FIG. 1 is a perspective view schematically illustrating a configurationexample of a solid state imaging device 1 according to a firstembodiment of the present technology. Incidentally, a description isgiven here taking a case where the solid state imaging device 1 is aCMOS image sensor as an example. However, the present technology is notlimited to the application to the CMOS image sensor.

The solid state imaging device 1 is a semiconductor chip with astructure where a pixel substrate 11 and a logic substrate 12 arestacked (what is called a stacked structure). Moreover, the solid stateimaging device 1 is a back-illuminated CMOS image sensor. Wiring layersof the pixel substrate 11 and wiring layers of the logic substrate 12are stacked in such a manner as to be adjacent to each other.Incidentally, the present technology is not limited to the applicationto the back-illuminated CMOS image sensor.

The pixel substrate 11 is a semiconductor substrate where a pixelcircuit 21 is formed, the pixel circuit 21 including a pixel array unit(pixel unit) 31 where unit pixels 32 each including a photoelectricconversion device are two-dimensionally arranged in a matrix. Moreover,although illustration is omitted, an edge portion surrounding the pixelarray unit 31 of the pixel circuit 21 is provided with, for example, apad for electrically connecting to the outside and a via forelectrically connecting to the logic substrate 12. A pixel signalobtained from each unit pixel 32 of the pixel array unit 31 is an analogsignal. This analog pixel signal is transmitted from the pixel substrate11 to the logic substrate 12 through the via and the like.

The logic substrate 12 is a semiconductor substrate that is formed insuch a manner as to arrange a signal processing circuit 41L and a rightsignal processing circuit 41R, both of which include the same circuitpattern, side by side across a scribe area 42. Incidentally in FIG. 1,the width of the scribe area 42 is exaggerated and illustrated largerthan actually it is to facilitate the understanding of FIG. 11. The sameshall apply to subsequent drawings.

The signal processing circuit 41L, for example, performs predeterminedsignal processing including digitization (AD conversion) on an analogpixel signal read out from each unit pixel 32 in a left-half area of thepixel array unit 31, and stores pixel data on which the signalprocessing has been performed. Moreover, the signal processing circuit41L, for example, reads out the stored pieces of pixel data in apredetermined order and outputs the data to the outside of the chip.Consequently, the signal processing circuit 41L outputs image dataobtained by the unit pixels 32 in the left-half area of the pixel arrayunit 31.

The signal processing circuit 41R, for example, performs predeterminedsignal processing including digitization (AD conversion) on an analogpixel signal read out from each unit pixel 32 in a right-half area ofthe pixel array unit 31, and stores pixel data on which the signalprocessing has been performed. Moreover, the signal processing circuit41R, for example, reads out the stored pieces of pixel data in apredetermined order and outputs the data to the outside of the chip.Consequently, the signal processing circuit 41R outputs image dataobtained by the unit pixels 32 in the right-half area of the pixel arrayunit 31.

Moreover, the signal processing circuits 41L and 41R, for example,control each unit of the solid state imaging device 1 in synchronizationwith the pixel circuit 21.

In this manner, with the stacked structure of the pixel substrate 11 andthe logic substrate 12, the area of the pixel substrate 11 can be madesubstantially equal to the area of the pixel array unit 31. As a result,the size of the solid state imaging device 1 can be reduced, which inturn can reduce the size of the entire chip. Moreover, the apertureratio of the solid state imaging device 1 can be increased.

Furthermore, a process suitable for the production of the unit pixel 32and the like can be applied to the pixel substrate 11, and a processsuitable for the production of the signal processing circuits 41L and41R to the logic substrate 12. Accordingly, upon the manufacture of thesolid state imaging device 1, process optimization can be promoted.

Incidentally, the area of the pixel circuit 21 is larger than theexposure field of an exposure apparatus. Therefore, split exposure isrequired. On the other hand, each of the areas of the signal processingcircuits 41L and 41R is smaller than the exposure field of the exposureapparatus. Therefore, one-shot exposure is possible.

Incidentally, if there is no need to distinguish the signal processingcircuits 41L and 41R individually, they are simply referred to as thesignal processing circuit 41 below.

{1-2. Circuit Configuration}

FIG. 2 is a circuit diagram illustrating specific configurations of thepixel circuit 21 on the pixel substrate 11 side of the solid stateimaging device 1, and the signal processing circuits 41L and 41R on thelogic substrate 12 side.

Incidentally, as described above, electrical connections between thepixel circuit 21 and the signal processing circuits 41L and 41R are madevia unillustrated vias.

(Configuration of the Pixel Circuit 21)

Firstly, the configuration of the pixel circuit 21 on the pixelsubstrate 11 side is described. The pixel circuit 21 is provided with arow selection unit 33 that selects the unit pixels 32 of the pixel arrayunit 31, row by row, using an address signal given from the logicsubstrate 12 side, in addition to the pixel array unit 31 where the unitpixels 32 are two-dimensionally arranged in a matrix. Incidentally, herethe row selection unit 33 is provided on the pixel substrate 11 side,but can also be provided on the logic substrate 12 side.

The unit pixel 32 includes, for example, a photodiode 51 as thephotoelectric conversion device. Moreover, the unit pixel 32 includes,for example, four transistors—a transfer transistor (transfer gate) 52,a reset transistor 53, an amplifying transistor 54, and a selecttransistor 55—in addition to the photodiode 51.

For example, N-channel transistors are used here as the four transistors52 to 55. However, the combination of the conductivity types of thetransfer transistor 52, the reset transistor 53, the amplifyingtransistor 54, and the select transistor 55 illustrated here is a mereexample, and the combination is not limited to this. In other words, acombination using a P-channel transistor can be used if needed.

The row selection unit 33 provides a transfer signal TRG, a reset signalRST, and a select signal SEL, which are drive signals to drive a unitpixel 32, to the unit pixel 32 as appropriate. In other words, thetransfer signal TRG is applied to a gate electrode of the transfertransistor 52, the reset signal RST to a gate electrode of the resettransistor 53, and the select signal SEL to a gate electrode of theselect transistor 55.

The photodiode 51 is connected at an anode electrode to a lowpotential-side power supply (for example, the ground), andphotoelectrically converts the received light (incident light) intophotocharge (photoelectrons, here) of a charge amount according to thelight quantity to accumulate the photocharge. A cathode electrode of thephotodiode 51 is electrically connected to a gate electrode of theamplifying transistor 54 via the transfer transistor 52. A node 56 thatis electrically coupled to the gate electrode of the amplifyingtransistor 54 is called a floating diffusion/floating diffusion region(FD) portion.

The transfer transistor 52 is connected between the cathode electrode ofthe photodiode 51 and the FD portion 56. The row selection unit 33provides the transfer signal TRG that is active at a high level (forexample, a V_(DD) level) (hereinafter described as “active-high”) to thegate electrode of the transfer transistor 52. In response to thistransfer signal TRG, the transfer transistor 52 becomes electricallyconductive to transfer the photocharge photoelectrically converted bythe photodiode 51 to the FD portion 56.

The reset transistor 53 is connected at a drain electrode to a pixelpower supply V_(DD) and at a source electrode to the FD portion 56. Therow selection unit 33 provides an active-high reset signal RST to thegate electrode of the reset transistor 53. In response to this resetsignal RST, the reset transistor 53 becomes electrically conductive,dumps the charge of the FD portion 56 into the pixel power supplyV_(DD), and accordingly resets the FD portion 56.

The amplifying transistor 54 is connected at the gate electrode to theFD portion 56 and at a drain electrode to the pixel power supply V_(DD).Then, the amplifying transistor 54 outputs the potential of the FDportion 56 that has been reset by the reset transistor 53 as a resetsignal (reset level) Vreset. The amplifying transistor 54 furtheroutputs the potential of the FD portion 56 whose signal charge has beentransferred by the transfer transistor 52 as a light accumulated signal(signal level) Vsig.

The select transistor 55 is connected, for example, at a drain electrodeto a source electrode of the amplifying transistor 54 and at a sourceelectrode to a signal line 34. The row selection unit 33 provides anactive-high select signal SEL to the gate electrode of the selecttransistor 55. In response to this select signal SEL, the selecttransistor 55 becomes electrically conductive to put the unit pixel 32in a selected state, and reads out a signal output from the amplifyingtransistor 54 to the signal line 34.

As is clear from the above-mentioned description, the potential of theFD portion 56 after resetting is read out as the reset level Vresetfirst and then the potential of the FD portion 56 after the transfer ofsignal charge is read out as the signal level Vsig, from the unit pixel32 to the signal line 34. Parenthetically, the signal level Vsig alsoincludes a component of the reset level Vreset.

Incidentally, here the circuit is configured to connect the selecttransistor 55 between the source electrode of the amplifying transistor54 and the signal line 34. However, it is also possible to adopt acircuit configuration where the select transistor 55 is connectedbetween the pixel power supply V_(DD) and the drain electrode of theamplifying transistor 54.

Moreover, the unit pixel 32 is not limited to the one with the abovepixel configuration including four transistors. For example, a pixelconfiguration including three transistors, in which the amplifyingtransistor 54 has the function of the select transistor 55, and a pixelconfiguration that shares transistors of the FD portion 56 and lateramong a plurality of photoelectric conversion devices (pixels) are alsoacceptable. The configuration of the pixel circuit does not matter.

(Configuration of the Signal Processing Circuits 41L and 41R)

Next, the configuration of the signal processing circuits 41L and 41R onthe logic substrate 12 side is described. Incidentally, as describedabove, the signal processing circuits 41L and 41R have the same circuitpattern. The configuration of the signal processing circuit 41L ismainly described here.

The signal processing circuit 41L is a circuit that mainly performsprocessing on pixel signals from the unit pixels 32 in the left-halfarea of the pixel array unit 31. The signal processing circuit 41L isconfigured including a current source 61L, a decoder 62L, a control unit63L, a row decoder 64L, a signal processing unit 65L, a columndecoder/sense amplifier 66L, a memory unit 67L, a data processing unit68L, and an interface (IF) unit 69L.

The current source 61L is connected to each signal line 34 where signalsare read out, on a pixel column basis, from each unit pixel 32 of thepixel array unit 31. The current source 61L has a configuration of whatis called a load MOS circuit including MOS transistors whose gatepotentials are biased to a constant potential in such a manner as tosupply a constant current to the signal line 34. The current source 61Lincluding the load MOS circuit supplies a constant current to anamplifying transistor 54 of a unit pixel 32 in the selected row tooperate the amplifying transistor 54 as a source follower.

Upon the selection of the unit pixels 32, row by row, in the pixel arrayunit 31, the decoder 62L provides an address signal that specifies anaddress of the selected row to the row selection unit 33 under controlby the control unit 63L.

The row decoder 64L specifies a row address under control by the controlunit 63L when the pixel data is written into the memory unit 67L andread out from the memory unit 67L.

The signal processing unit 65L includes at least AD converters 81L-1 to81L-n that digitize an analog pixel signal read out from each unit pixel32 of the pixel array unit 31 through the signal line 34 (ADconversion). In addition, the signal processing unit 65L is configuredto perform signal processing on the analog pixel signals in parallel ona pixel column basis (column parallel AD). Incidentally, if there is noneed to distinguish the AD converters 81L-1 to 81L-n individually, theyare simply referred to as the AD converter 81L below.

The signal processing unit 65L further includes a reference voltagegeneration unit 82L that generates a reference voltage to be used uponAD conversion in each AD converter 81L. The reference voltage generationunit 82L generates a reference voltage of what is called a ramp (RAMP)waveform (an inclined waveform) where a voltage value changes stepwisewith the passage of time. The reference voltage generation unit 82L canbe configured using, for example, a digital-to-analog converter (DAC)circuit.

The AD converter 81L is provided to, for example, each column of pixelsof the pixel array unit 31, that is, each signal line 34. In otherwords, the AD converter 81L is what is called a column parallel ADconverter where the AD converter 81L is placed at each column of thepixels in the left half of the pixel array unit 31. In addition, each ADconverter 81L, for example, generates a pulse signal with an amplitude(pulse width) in a time axis direction corresponding to the level of theamplitude of a pixel signal, measures the length of the duration of thepulse width of the pulse signal, and accordingly performs an ADconversion process.

More specifically, for example, the AD converter 81L-1 is configuredincluding at least a comparator (COMP) 91L-1 and a counter 92L-1 asillustrated in FIG. 2. The comparator 91L-1 sets the analog pixel signal(the above-mentioned signal level Vsig or reset level Vreset) read outfrom the unit pixel 32 through the signal line 34 as a comparison input,and a reference voltage Vref of a ramp wave supplied from the referencevoltage generation unit 82L as a reference input to compare both inputs.

Then, in terms of the comparator 91L-1, for example, when the referencevoltage Vref is larger than the pixel signal, an output is in a firststate (for example, at a high level), and when the reference voltageVref is equal to or less than the pixel signal, an output is in a secondstate (for example, at a low level). An output signal of the comparator91L-1 is a pulse signal with a pulse width corresponding to the level ofthe amplitude of the pixel signal.

For example, an up/down counter is used for the counter 92L-1. A clockCK is provided to the counter 92L-1 at the same timing as the timing tostart supplying the reference voltage Vref to the comparator 91L. Thecounter 92L-1 being the up-down counter counts up (UP) or down (DOWN) insynchronization with the clock CK to measure the duration of the pulsewidth of the output pulse of the comparator 91L-1, that is, a comparisonperiod from the start to the end of the comparison operation. In termsof the reset level Vreset and the signal level Vsig, which are read outsequentially from the unit pixel 32, the counter 92L-1 counts down forthe reset level Vreset and counts up for the signal level Vsig upon themeasurement operation.

With the count-up/count-down operation, it is possible to take adifference between the signal level Vsig and the reset level Vreset. Asa result, the AD converter 81L-1 performs a correlated double sampling(correlated double sampling) (CDS) process, in addition to the ADconversion process. The CDS process here is a process of taking thedifference between the signal level Vsig and the reset level Vreset toremove reset noise of the unit pixel 32 and fixed pattern noise uniqueto a pixel such as the threshold variation of the amplifying transistor54. Then, the count result (count value) of the counter 92L-1 becomes adigital value obtained by digitizing the analog pixel signal.

Incidentally, the AD converters 81L-2 to 81L-n also have a similarconfiguration to the AD converter 81L-1. Their descriptions are omittedsince they are repetitive. Moreover, in the following description, ifthere is no need to distinguish the comparators 91L-1 to 91L-nindividually, they are simply referred to as the comparator 91L, and ifthere is no need to distinguish the counters 92L-1 to 92L-nindividually, they are simply referred to as the counter 92L.

FIG. 3 is a block diagram illustrating an example of a specificconfiguration of the signal processing unit 65L. The signal processingunit 65L includes a data latch unit 83L and a parallel-to-serial(hereinafter abbreviated as “P/S”) conversion unit 84L in addition tothe AD converter 81L and the reference voltage generation unit 82L. Inaddition, the signal processing unit 65L has a pipeline configurationwhere pixel data digitized by the AD converter 81L is pipelinetransferred to the memory unit 67L. At this point in time, the signalprocessing unit 65L performs a digitization process by the AD converter81L in one horizontal period, and performs a process of transferring thedigitized pixel data to the data latch unit 83L in the next horizontalperiod.

On the other hand, the memory unit 67L is provided with the columndecoder/sense amplifier 66L as its peripheral circuit. Theabove-mentioned row decoder 64L (see FIG. 2) specifies a row address forthe memory unit 67L, whereas the column decoder specifies a columnaddress for the memory unit 67L. Moreover, the sense amplifier amplifiesa weak voltage readout from the memory unit 67L through a bit line to alevel where it can be handled as a digital level. The pixel data readout through the column decoder/sense amplifier 66L is then output to theoutside of the logic substrate 12 via the data processing unit 68L andthe interface unit 69L.

Incidentally, here the case where the number of the column parallel ADconverters 81L is one is taken as an example. The number of the columnparallel AD converters 81L is not limited to one. A configuration canalso be adopted in which two or more AD converters 81L are provided toperform the digitization process in parallel in the two or more ADconverters 81L.

In this case, the two or more AD converters 81L are placed divided in,for example, the extension direction of the signal line 34 of the pixelarray unit 31, that is, into both of the upper and lower sides of thepixel array unit 31. If two or more AD converters 81L are provided, twoor more (systems of) data latch units 83L, P/S conversion units 84L,memory units 67L, and the like are also provided accordingly.

In this manner, in the solid state imaging apparatus 1 that adopts aconfiguration where, for example, two systems of the AD converters 81Land the like are provided, every two rows of pixels are scanned inparallel. Then, a signal of each pixel of one pixel row and a signal ofeach pixel of the other pixel row are read out to one side in theup-and-down direction of the pixel array unit 31 and the other side inthe up-and-down direction of the pixel array unit 31, respectively. Thetwo AD converters 81L perform the digitization process on them inparallel. Subsequent signal processing is also similarly performed inparallel. As a result, the pixel data is read out at a higher speed thana case where one pixel row is scanned at a time.

Incidentally, although detailed illustration and description areomitted, the signal processing circuit 41R also has a similarconfiguration to the signal processing circuit 41L. In addition, thesignal processing circuit 41R mainly performs processing on pixelsignals from the unit pixels 32 in the right-half area of the pixelarray unit 31.

Incidentally, a reference sign of each unit of the signal processingcircuit 41R, the illustration of which is omitted, is a reference signhaving the letter R replaced with L included in a reference sign of eachunit of the signal processing circuit 41L below.

{1-3. Layout of the Logic Substrate 12}

FIG. 4 illustrates an example of the layout of the logic substrate 12.As illustrated in FIG. 4, the signal processing circuits 41L and 41R ofthe logic substrate 12 have the same and left-right symmetric layout.

In the signal processing circuit 41L, an AD conversion unit 101L-1, amemory unit 102L-1, a logic unit 103L, a memory unit 102L-2, and an ADconversion unit 101L-2 are stacked sequentially from the top. Moreover,an interface unit 104L-1 and an interface unit 104L-2 are placed on theleft and right of the stacked unit. Furthermore, vias 105L-1 to 105L-4are placed respectively at upper, lower, left and right edges of thesignal processing circuit 41L.

For example, the current sources 61L, the AD converters 81L-1 to 81L-n,the reference voltage generation units 82L, the data latch units 83L,and the P/S conversion units 84L illustrated in FIGS. 2 and 3 aredivided and placed in the AD conversion units 101L-1 and 101L-2.

Incidentally, in this example, three layers each including the ADconverter 81L and a circuit part accompanied by the AD converter 81L arestacked and placed in each of the AD conversion units 101L-1 and 101L-2.In other words, in the signal processing circuit 41L, the AD converters81L and the accompanied circuit parts are placed divided into sixsystems. In addition, the signal processing circuit 41L scans, forexample, every six pixel rows in parallel.

Moreover, pixel signals from the unit pixels 32 of the pixel array unit31 are supplied to the AD converter 81L placed in the AD conversionunits 101L-1 and 101L-2 via the vias 105L-1 to 105L-4.

For example, the column recorder/sense amplifier 66L and the memory unit67L, which are illustrated in FIG. 3, are placed in each of the memoryunits 102L-1 and 102L-2. In addition, pixel data supplied from the ADconversion unit 101L-1 is stored in the memory unit 102L-1, and pixeldata supplied from the AD conversion unit 101L-2 is stored in the memoryunit 102L-2.

For example, the decoder 62L, the control unit 63L, the row decoder 64L,and the data processing unit 68L, which are illustrated in FIG. 2, areplaced in the logic unit 103L.

For example, the interface unit 69L illustrated in FIG. 2 is placed ineach of the interface units 104L-1 and 104L-2.

Incidentally, the signal processing circuit 41R has the same layout asthe signal processing circuit 41L. The description is omitted since itis repetitive.

Moreover, the above-mentioned configuration and layout of the signalprocessing circuits 41L and 41R are examples. Configurations and layoutsother than the above mentioned ones can also be adopted.

{1-4. Imaging Process of the Solid State Imaging Device 1}

Next, an imaging process of the solid state imaging device 1 is brieflydescribed with reference to FIGS. 5 and 6.

FIG. 5 illustrates an example of a method for connecting the signalprocessing circuits 41L and 41R of the solid state imaging device 1 andan external signal processing LSI 121. Specifically, the interface unit104L-1 of the signal processing circuit 41L and an interface unit 104R-2of the signal processing circuit 41R are connected to the signalprocessing LSI 121.

If, for example, an object 141 of FIG. 6 is imaged with the solid stateimaging device 1, pixel signals from the unit pixels 32 in the left-halfarea of the pixel array unit 31 are supplied to the signal processingcircuit 41L, and pixel signals from the unit pixels 32 in the right-halfarea to the signal processing circuit 41R. In other words, pixel signalscorresponding to the left half of the object 141 are supplied to thesignal processing circuit 41L, and pixel signals corresponding to theright half of the object 141 to the signal processing circuit 41R.

The signal processing circuit 41L generates image data 142Lcorresponding to the left half of the object 141, using the pixelsignals supplied from the pixel circuit 21. Similarly, the signalprocessing circuit 41R generates image data 142R corresponding to theright half of the object 141, using the pixel signals supplied from thepixel circuit 21.

The signal processing circuit 41L then outputs the generated image data142L from the interface unit 104L-1, and supplies the image data 142L tothe signal processing LSI 121. The signal processing circuit 41R outputsthe generated image data 142R from the interface unit 104R-2, andsupplies the image data 142R to the signal processing LSI 121.

The signal processing LSI 121 combines the image data 142L and the imagedata 142R, generates one sheet of image data 143, and outputs thegenerated image data 143.

In this manner, left and right sets of image data are generatedindependently in the solid state imaging device 1. Accordingly,processing speed can be increased.

{1-5. Method for Setting the Left and Right Signal Processing Circuits41}

As described above, the signal processing circuits 41 have a commoncircuit pattern and the same functions. On the other hand, as describedabove, the signal processing circuit 41L generates image data of theleft half of an object and outputs the generated image data from theleft interface unit 104L-1. Moreover, the signal processing circuit 41Rgenerates image data of the right half of the object, and outputs thegenerated image data from the right interface unit 104R-2. In otherwords, the signal processing circuit 41L operates as a circuit placed onthe left side of the logic substrate 12, and the signal processingcircuit 41R operates as a circuit placed on the right side of the logicsubstrate 12.

Hence, each signal processing circuit 41 has the functions of both ofthe left signal processing circuit 41L and the right signal processingcircuit 41R to be able to operate as both of them. In addition, anexternal signal sets each signal processing circuit 41 regarding whetherto operate as the left signal processing circuit 41L or the right signalprocessing circuit 41R. To put another way, the external signal sets thefunctions of each signal processing circuit 41 to enabled and disabled,respectively.

Specifically, for example, the signal processing circuits 41L and 41Rare connected to an external substrate 161 respectively by bonding wires162L and 162R as illustrated schematically in FIG. 7. Incidentally, thissubstrate 161 may be provided within the same package as the solid stateimaging device 1, or may be provided outside the package.

In addition, the substrate 161 supplies a select signal to the signalprocessing circuit 41L via a bonding wire 162L. The select signal takes,for example, a value of a power supply level (High) or ground level(Low). The signal processing circuit 41L includes multiplexer 171L and acore 172L, which are illustrated in FIG. 8. The select signal from thesubstrate 161 is then input into the multiplexer 171L. The multiplexer171L supplies, to the core 172L, a setting signal indicating the value 0or 1 in accordance with the select signal.

The setting signal has the value 0 if a setting is performed for theleft circuit (the signal processing circuit 41L), and has the value 1 ifa setting is performed for the right circuit (the signal processingcircuit 41R). The core 172L then stores the value of the setting signalin an unillustrated register. The signal processing circuit 41L operatesin accordance with the value of the register. For example, the value ofthe register of the signal processing circuit 41L is set to 0, and thesignal processing circuit 41L then operates as the left signalprocessing circuit.

Incidentally, although illustration is omitted, the signal processingcircuit 41R is also provided with a multiplexer 171R and a core 172R asin the signal processing circuit 41L. The signal processing circuit 41Ris then set by a select signal supplied from the substrate 161 via thebonding wire 162R in a similar method to the signal processing circuit41L to operate as the right signal processing circuit.

Moreover, the signal processing circuits 41L and 41R have the samefunctions so that the functions are redundant. Hence, in terms offunctions that suffice if only one of them operates, this select signalenables those of one of the signal processing circuits 41 and disablesthose of the other signal processing circuit 41.

{1-6. Method for Manufacturing the Solid State Imaging Device 1}

Next, a method for manufacturing the solid state imaging device 1 isdescribed with reference to FIGS. 9 to 13. Incidentally, in FIGS. 9 to13, only the pixel circuits 21 and the signal processing circuits 41 areillustrated and the illustration of wafers (semiconductor substrates) onwhich the pixel circuits 21 and the signal processing circuits 41 areformed is omitted to facilitate the understanding of FIGS. 9 to 13.

Firstly, as illustrated in FIG. 9, pixel circuits 21-1 and 21-2, . . .are formed on the unillustrated wafer (semiconductor substrate). At thispoint in time, the area of each pixel circuit 21 is larger than theexposure field of the exposure apparatus. Therefore, split exposure isused for the exposure of each pixel circuit 21.

Moreover, scribe areas 22 are provided between adjacent pixel circuits21 in a longitudinal direction and a lateral direction. Incidentally, inFIG. 9, the width of the scribe area 22 is exaggerated and illustratedlarger than actually it is to facilitate the understanding of FIG. 9.The same shall apply to the subsequent drawings.

Moreover, in FIG. 9, only two pixel circuits 21 in two rows and onecolumn are illustrated. However, in reality more pixel circuits 21 areformed in such a manner as to be two-dimensionally arranged.

Moreover, with a manufacturing process different from FIG. 9, signalprocessing circuits 41L-1, 41R-1, 41L-2, 42R-2, . . . are formed on theunillustrated wafer (semiconductor substrate) as illustrated in FIG. 10.Of them, the signal processing circuits 41L-1 and 41R-1 are placed inthe same logic substrate 12, and the signal processing circuits 41L-2and 41R-1 are placed in the same logic substrate 12. At this point intime, the area of each signal processing circuit 41 is smaller than theexposure field of the exposure apparatus. Accordingly, one-shot exposureis used for the exposure of each signal processing circuit 41.

Moreover, scribe areas 42 are provided between adjacent signalprocessing circuits 41 in a longitudinal direction and a lateraldirection. Naturally the scribe area 42 is also provided between thesignal processing circuits 41 placed in the same logic substrate 12.

Moreover, in FIG. 10, only four signal processing circuits 41 in tworows and two columns are illustrated. However, in reality more signalprocessing circuits 41 are formed in such a manner as to betwo-dimensionally arranged.

Next, as illustrated in FIG. 11, the wafer on which the pixel circuits21 are formed (hereinafter referred to as the pixel wafer) and the waferon which the signal processing circuits 41 are formed (hereinafterreferred to as the logic wafer) are bonded to stack the pixel wafer andthe logic wafer.

Here the area of the signal processing circuits 41 adjacent side by sideacross the scribe area 42 is substantially the same as that of the pixelcircuit 21. The pixel wafer and the logic wafer are stacked in such amanner as to superpose the scribe area 22 of the pixel wafer on thescribe area 42 of the logic wafer. Consequently, the pixel circuit 21 isprecisely overlaid on the signal processing circuits 41 that areadjacent side by side. For example, the pixel circuit 21-1 is preciselyoverlaid on the signal processing circuits 41L-1 and 41R-2 that areadjacent side by side across the scribe area 42.

Moreover, the solid state imaging device 1 is back illuminated. Thepixel wafer and the logic wafer are stacked such that a substrate layerwhere the pixel circuits 21 of the logic wafer are formed faces up andwiring layers of the logic wafer and wiring layers of the pixel waferare adjacent to each other.

Incidentally, the wafer obtained by stacking the pixel wafer and thelogic wafer is referred to as the stacked wafer below.

Next, as indicated by bold dotted lines of FIG. 12, the stacked wafer iscut into chips. In other words, the stacked wafer is cut along thescribe areas 22, provided around the pixel circuits 21, of the pixelwafer. Incidentally, the scribe areas 42 of the logic wafer that are notsuperposed on the scribe areas 22 of the pixel wafer are left uncut asthey are.

Consequently, the solid state imaging device where the pixel circuit 21is stacked on the signal processing circuits 41 adjacent side by sidewith the uncut scribe area 42 is separated as a single piece. Forexample, as illustrated in FIG. 13, a solid state imaging device 1-1where the pixel circuit 21-1 is stacked on the signal processingcircuits 41L-1 and 41R-1 adjacent across the scribe area 42 is separatedas a single piece.

In this manner, even if the area of the pixel circuit 21 on the pixelsubstrate 11 side is larger than the exposure field of the exposureapparatus and therefore split exposure is required, each signalprocessing circuit 41 on the logic substrate 12 side is manufactured byone-shot exposure without using split exposure. Moreover, the signalprocessing circuits 41 with the same circuit pattern are formed in sucha manner as to be two-dimensionally arranged, leaving a predeterminedspace (the scribe area 42) therebetween, irrespective of on which of theleft and right sides of the solid state imaging device 1 each signalprocessing circuit 41 is placed. Therefore, for example, it is possibleto reduce the number of types of photomasks required to manufacture thelogic substrate 12 and also manufacture the logic substrate 12 with anexposure apparatus that does not have a photomask replacement apparatus.

2. Second Embodiment

As described above, in the solid state imaging device 1, two signalprocessing circuits are not electrically connected, and performprocessing independently of each other. In contrast, in a secondembodiment of the present technology, two signal processing circuits areelectrically connected and perform part of the processing incoordination.

{2-1. System Configuration}

FIG. 14 is a perspective view schematically illustrating a configurationexample of a solid state imaging device 201 according to the secondembodiment of the present technology. Incidentally, in FIG. 14, the samereference signs are assigned to portions corresponding to FIG. 1 and thedescription of portions that perform the same processes is omitted asappropriate since it is repetitive.

As illustrated in FIG. 14, the solid state imaging device 201 is asemiconductor chip with a structure where the pixel substrate 11 and alogic substrate 211 are stacked (what is called a stacked structure) asin the solid state imaging device 1.

The logic substrate 211 is different from the logic substrate 12 inthat, instead of the signal processing circuits 41L and 41R, signalprocessing circuits 241L and 241R are provided. Moreover, the logicsubstrate 211 is different from the logic substrate 12 in that a wiringlayer for electrically connecting the signal processing circuits 241Land 241R (hereinafter referred to as the inter-circuit wiring layer) isformed in the uppermost layer of the logic substrate 12. In other words,shaded patterns on the logic substrate 211 of FIG. 14 indicate wiringpatterns of the inter-circuit wiring layer. The signal processingcircuits 241L and 241R are electrically connected in this inter-circuitwiring layer.

Moreover, the signal processing circuits 241L and 241R are different inpart of the layout from the signal processing circuits 41L and 41R asdescribed below with reference to FIG. 15.

Incidentally, if there is no need to distinguish the signal processingcircuits 241L and 241R individually, they are simply referred to as thesignal processing circuit 241 below.

{2-2. Layout of the Logic Substrate 211}

FIG. 15 illustrates an example of the layout of the logic substrate 211.Incidentally, in FIG. 15, the illustration of the inter-circuit wiringlayer is omitted. Moreover, in FIG. 15, the same reference signs areassigned to portions corresponding to FIG. 4. The description ofportions that perform the same processes and the like is omitted asappropriate.

The signal processing circuit 241L is different from the signalprocessing circuit 41L of FIG. 4 in that the interface unit 104L-1 iseliminated and only the interface unit 104L-2 is provided. Similarly,the signal processing circuit 241R is different from the signalprocessing circuit 41R of FIG. 4 in that the interface unit 104R-1 iseliminated and only the interface unit 104R-2 is provided.

{2-3. Imaging Process of the Solid State Imaging Device 201}

Next, an imaging process of the solid state imaging device 201 isbriefly described with reference to FIGS. 6 and 15.

If, for example, the object 141 of FIG. 6 is imaged with the solid stateimaging device 201, pixel signals from the unit pixels 32 in theleft-half area of the pixel array unit 31 are supplied to the signalprocessing circuit 241L. Pixel signals from the unit pixels 32 in theright-half area are supplied to the signal processing circuit 241R. Inother words, pixel signals corresponding to the left half of the object141 are supplied to the signal processing circuit 241L, and pixelsignals corresponding to the right half of the object 141 are suppliedto the signal processing circuit 241R.

The signal processing circuit 241L generates the image data 142Lcorresponding to the left half of the object 141, using the pixelsignals supplied from the pixel circuit 21. Similarly, the signalprocessing circuit 241R generates the image data 142R corresponding tothe right half of the object 141, using the pixel signals supplied fromthe pixel circuit 21.

The processing up to this point is similar to the above-mentioned solidstate imaging device 1.

The logic unit 103L of the signal processing circuit 241L then suppliesthe generated image data 142L to a logic unit 103R of the signalprocessing circuit 241R via the unillustrated inter-circuit wiringlayer.

The logic unit 103R combines the image data 142L supplied from thesignal processing circuit 241L and the image data 142R created byitself, and generates one sheet of the image data 143. The logic unit103R then outputs the generated image data 143 to the outside via theinterface unit 104R-2.

In this manner, the solid state imaging device 201 can generate andoutput one complete sheet of image data without using a device such asan external LSI unlike the solid state imaging device 1. Therefore, thenecessity of providing the signal processing LSI 121 externally iseliminated; accordingly, cost reduction can be promoted.

Incidentally, also in the solid state imaging device 201, the signalprocessing circuits 241L and 241R are set regarding whether to operateas the left or right side signal processing circuit, by the methoddescribed above with reference to FIGS. 7 and 8 as in the solid stateimaging device 1.

[Method for Manufacturing the Solid State Imaging Device 201]

Next, a method for manufacturing the solid state imaging device 201 isdescribed with reference to the above-illustrated FIGS. 9 and 10, andFIGS. 16 to 19. Incidentally, in FIGS. 16 to 19, only the pixel circuits21 and the signal processing circuits 241 are illustrated and theillustration of wafers (semiconductor substrates) of the pixel circuits21 and the signal processing circuits 241 are formed is omitted tofacilitate the understanding of FIGS. 16 to 19 as in FIGS. 9 to 13.

Firstly, a pixel wafer on which the pixel circuits 21 aretwo-dimensionally arranged across the scribe areas 22, and a logic waferon which the signal processing circuits 241 are two-dimensionallyarranged across the scribe areas 42 are manufactured in a similar methodto the method described above with reference to FIGS. 9 and 10.

Next, as illustrated in FIG. 16, the inter-circuit wiring layer isformed in the uppermost layer of the logic wafer. Incidentally, theinter-circuit wiring layer is of substantially the same size as thepixel circuit 21 of the pixel substrate 11 and accordingly is formedusing split exposure. The inter-circuit wiring layer connects two signalprocessing circuits 241 (for example, signal processing circuits 241L-1and 241R-1) placed in the same solid state imaging device 201electrically.

Incidentally, for example, a manufacturer who manufactures logic wafersmay manufacture a logic wafer before exposure on which a metal film forthe inter-circuit wiring layer has simply been deposited, and deliver itto a manufacture who manufactures the solid state imaging devices 201.Then, for example, the manufacturer who manufactures the solid stateimaging devices 201 may form the inter-circuit wiring layer of the logicwafer by split exposure and then stack the pixel wafer and the logicwafer. Consequently, even a manufacturer who does not have a facilityfor split exposure can manufacture the logic wafer.

Next, as illustrated in FIG. 17, the pixel wafer and the logic wafer arestacked as in the manufacturing process described above with referenceto FIG. 11.

As illustrated in FIG. 18, the stacked wafer is then cut into chips asin the manufacturing process described above with reference to FIG. 12.Consequently, for example, a solid state imaging device 201-1 where thepixel circuit 21-1 is stacked on the signal processing circuits 241L-1and 241R-1 that are adjacent across the scribe area 42 is separated asone piece as illustrated in FIG. 19.

Incidentally, in the above-mentioned example, the example where theinter-circuit wiring layer is formed in the uppermost layer of the logicsubstrate 211 is illustrated. However, the inter-circuit wiring layermay be formed in a layer below the uppermost layer. If, for example, aplurality of wiring layers is provided to the signal processing circuit241, the signal processing circuits 241L and 241R may be connected in awiring layer formed below the uppermost layer of the logic substrate211.

Moreover, for example, the signal processing circuits 241L and 241R maybe connected via a plurality of wiring layers. In other words, aplurality of inter-circuit wiring layers may be formed. Furthermore, notonly a wire for connecting the signal processing circuits 241L and 241Rbut also a wire in each signal processing circuit 241 (for example, awire between devices) can also be provided in the inter-circuit wiringlayer.

Moreover, also if the inter-circuit wiring layer is placed in any oflayers of the logic substrate 211, among the layers of the logicsubstrate 211, for example, the inter-circuit wiring layer is formed bysplit exposure and the other layers are formed by one-shot exposure.

Incidentally, if the inter-circuit wiring layer is formed by a differentmanufacturer as described above, the inter-circuit wiring layer isdesired to be formed in the uppermost layer of the logic substrate 211.

3. Third Embodiment

In a third embodiment of the present technology, left and right signalprocessing circuits are electrically connected by a different methodfrom the one of the second embodiment.

Specifically, FIG. 20 is a perspective view schematically illustrating aconfiguration example of a solid state imaging device 301 according tothe third embodiment of the present technology. The solid state imagingdevice 301 is a semiconductor chip with a structure where a pixelsubstrate 311 (FIG. 21) in which a pixel circuit 321 is formed and alogic substrate 312 (FIG. 21) in which signal processing circuits 341Land 341R are formed are stacked (what is called a stacked structure) asin the solid state imaging devices 1 and 201.

A pixel array unit 331 similar to the pixel array unit 31 of the pixelcircuit 21 of FIG. 1 is formed in the pixel circuit 321. Moreover, thepixel circuit 321 has a circuit configuration similar to that of thepixel circuit 21 described above with reference to FIG. 2. The signalprocessing circuits 341L and 341R have a similar circuit configurationto that of the signal processing circuits 41L and 41R described abovewith reference to FIGS. 2 and 3. The logic substrate 312 has a similarlayout to that of the logic substrate 12 described above with referenceto FIG. 4. In this manner, the solid state imaging device 301 has asubstantially similar circuit configuration and layout to those of thesolid state imaging device 1.

However, the solid state imaging device 301 is different from the solidstate imaging device 1 in that the signal processing circuits 341L and341R are electrically connected in the pixel substrate 311.

Specifically, FIG. 21 illustrates an A-A cross-sectional view of thesolid state imaging device 301 of FIG. 20. In other words, FIG. 21illustrates a cross section of the solid state imaging device 301outside the pixel array unit 331 of the pixel circuit 321 and on thefront side in FIG. 20.

The solid state imaging device 301 is a back-illuminated imaging device;accordingly, the pixel substrate 311 and the logic substrate 312 arestacked in such a manner that their wiring layers are adjacent to eachother. Therefore, a substrate layer of the pixel substrate 311 is placedon the top side and a substrate layer of the logic substrate 312 isplaced on the bottom side.

Wires 351L and 351R are formed outside the pixel array unit 331 on thesubstrate layer of the pixel substrate 311. The wire 351L is placedabove the signal processing circuit 341L. The wire 351R is placed abovethe signal processing circuit 341R.

In addition, the wire 351L is connected to a wiring layer of the signalprocessing circuit 341L via a via 352L formed in the pixel substrate311. Moreover, the wire 351L is connected to a wire 354L via a via 353L.The wire 354L is connected to a wire 356L via a via 355L. The wire 356Lis connected to a wire 358 via a via 357L.

The wire 351R is connected to a wiring layer of the signal processingcircuit 341R via a via 352R formed in the pixel substrate 311. Moreover,the wire 351R is connected to a wire 354R via a via 353R. The wire 354Ris connected to a wire 356R via a via 355R. The wire 356R is connectedto the wire 358 via a via 357R.

Consequently, the wiring layer of the signal processing circuit 341L andthe wiring layer of the signal processing circuit 341R are electricallyconnected via the via 352L, the wire 351L, the via 353L, the wire 354L,the via 355L, the wire 356L, the via 357L, the wire 358, the via 357R,the wire 356R, the viva 355R, the wire 354R, the via 353R, the wire351R, and the via 352R.

Therefore, the solid state imaging device 301 can also generate andoutput one sheet of image data obtained by imaging an object by themethod described above with reference to FIGS. 6 and 15, as in the solidstate imaging device 201.

Incidentally, the wires 351L and 351R, the vias 352L and 352R, and thelike of the pixel circuit 321 are formed upon, for example, themanufacture of the pixel wafer described above with reference to FIG. 9.

Moreover, the number of wiring layers of the pixel substrate 311 of FIG.21 is an example of the number of wiring layers and can be set to anygiven number. Furthermore, for example, the wire 358 for electricallyconnecting the signal processing circuits 341L and 341R in the wiringlayer of the pixel substrate 311 may be provided in any wiring layer ofthe pixel substrate 311, and also, for example, may be formed dividedinto a plurality of wiring layers.

<4. Modifications>

Modifications of the above-mentioned embodiments of the presenttechnology are described below.

{5-1. Modifications Related to the Configuration of the Solid StateImaging Device} (Modification Related to the Logic Substrate)

In the above description, the example where two signal processingcircuits are provided to the logic substrate is illustrated. However,three or more signal processing circuits can also be provided.

Moreover, the circuit patterns and sizes of all signal processingcircuits provided to one logic substrate are not necessarily required tobe the same. Signal processing circuits respectively having differentcircuit patterns and sizes can also be coresident. However, themanufacturing process is simpler and therefore the manufacturing cost islower if signal processing circuits having the same circuit pattern areprovided to the logic substrate than if signal processing circuitshaving different circuit patterns and sizes are coresident.

(Modification Related to the Stacked Structure)

Moreover, in the above description, the example is illustrated in whichthe solid state imaging device has a dual-layer stacked structureincluding the pixel substrate and the logic substrate. However, thepresent technology can also be applied to a solid state imaging deviceof a stacked structure of three or more layers. For example, anotherlogic substrate may be further stacked below the logic substrate 12 ofFIG. 1 (that is, a surface, which is opposite to a surface adjacent tothe pixel substrate 11, of the logic substrate 12). In this case, forexample, it is conceivable to place the memory units 102L-1 to 102R-2included in the signal processing circuits 41L and 41R in the addedlogic substrate in the lowermost layer.

Moreover, if two or more logic substrate layers are provided, the logicsubstrates in all the layers are not necessarily required to bemanufactured using one-shot exposure. Part of the logic substrates maybe manufactured using split exposure. For example, in theabove-mentioned example, the logic substrate in the lowermost layerprovided with the memory units 102L-1 to 102R-2 may be manufacturedusing split exposure.

Furthermore, as described above, the logic substrates in all the layersare not necessarily required to be manufactured using one-shot exposureif, for example, signal processing circuits are connected in the logicsubstrates, and part of the layers may be manufactured using splitexposure.

(Modification Related to a Method for Connecting the Signal ProcessingCircuits)

Furthermore, in the second and third embodiments of the presenttechnology, the example is illustrated in which the left and rightsignal processing circuits are electrically connected in the solid stateimaging device. However, the left and right signal processing circuitsmay be connected outside the solid state imaging device.

FIG. 22 illustrates an example where the signal processing circuits 41Land 41R of the solid state imaging device 1 are connected outside thesolid state imaging device 1. Incidentally, in this example, the solidstate imaging device 1 is housed in a package 401. Moreover, in FIG. 22,only the signal processing circuits 41L and 41R of the solid stateimaging device 1 are illustrated to facilitate the understanding of FIG.22.

The signal processing circuit 41L is connected to a conductive pattern412 formed in the package 401 via a bonding wire 411L. Similarly, thesignal processing circuit 41R is connected to the conductive pattern 412via a bonding wire 411R. Therefore, the signal processing circuits 41Land 41R are electrically connected via the bonding wires 411L and 411Rand the conductive pattern 412.

Incidentally, in addition to this, the signal processing circuits 41Land 41R may be electrically connected outside via a lead frame and thelike.

Moreover, the number of mountable wires is limited if the signalprocessing circuits 41L and 41R are connected outside the solid stateimaging device 1 as compared to if they are connected inside. Hence, itis assumed that it may be difficult to combine left and right sets ofimage data in the solid state imaging device 1. In this case, forexample, a signal line of a predetermined same analog signal between thesignal processing circuits 41L and 41R (for example, a reference voltagesignal line or a ground line) may be connected to achieve commonality ofthe analog signal.

For example, if different signal processing circuits 41 generate leftand right sets of image data, differences may occur in color andbrightness between the left and right sets of image data due todifferences in the characteristics and the like of each signalprocessing circuit 41; accordingly, the boundary of the combined portionof the two sets of image data may be visible. Hence, commonality of thepredetermined analog signal of each signal processing circuit 41 isachieved to enable a reduction in differences in the characteristics andthe like of each signal processing circuit 41 and the boundary of thecombined portion of the image data to become inconspicuous.

(Modification Related to an AD Conversion Technology)

Furthermore, in the above description, the example is illustrated inwhich a column parallel AD conversion technology is adopted for thesolid state imaging device as described above with reference to FIG. 2.However, a pixel AD parallel conversion technology may be adopted.

FIG. 23 schematically illustrates the configurations of a pixelsubstrate 511 and a logic substrate 512 of when the pixel AD conversiontechnology is adopted.

A pixel circuit 521 including a pixel array unit 531 is formed in thepixel substrate 511 as in the pixel substrate 11 of FIG. 1. Moreover,signal processing circuits 541L and 541R with the same circuit patternare formed in the logic substrate 512 in such a manner as to be arrangedside by side across the scribe area 42 as in the logic substrate 12 ofFIG. 1.

In addition, pixel units (groups) where an area including atwo-dimensional array with a predetermined number of pixels is set asone unit are two-dimensionally arranged in a matrix in the pixel arrayunit 531 of the pixel substrate 511. A via 532 is formed for each pixelunit. On the other hand, a circuit part (a pixel AD unit in FIG. 23)including, for example, the AD converter 81 (FIG. 2) and the memory unit67 (FIG. 2) is provided to each pixel unit of the pixel array unit 531in the signal processing circuits 541L and 541R. Moreover, a via 23corresponding to the pixel unit is formed for each pixel AD unit.

In this manner, the pixel parallel AD conversion technology is adoptedto enable an increase in the reading speed of a pixel signal.Accordingly, the halt period of the AD converter 81 can be increased. Asa result, a reduction in power consumption can be promoted.

(Modifications Related to a Moisture-Resistant Ring)

A moisture-resistant ring (also referred to as a sealing ring, a guardring, and the like) of the logic substrate can be basically formed by asimilar method to a known one. For example, the moisture-resistant ringis formed by a similar method to the known one in such a manner as tosurround the periphery of each signal processing circuit individually.However, if the inter-circuit wiring layer that connects the signalprocessing circuits electrically is formed in the logic substrate as inthe second embodiment described above with reference to FIG. 14 and thelike, when a moisture-resistant ring is formed by a similar method tothe known one, a wire in the inter-circuit wiring layer and themoisture-resistant ring interfere with each other. In other words, in aportion where a wire in the inter-circuit wiring layer passes an edge ofthe signal processing circuit, a moisture-resistant ring formed at theedge of the inter-circuit wiring layer and the wire in the inter-circuitwiring layer interfere with each other.

Hence, a method for avoiding interference between a wire in theinter-circuit wiring layer and a moisture-resistant ring is describedbelow.

Firstly, a first method for avoiding interference between a wire in theinter-circuit wiring layer and a moisture-resistant ring is describedwith reference to FIGS. 24 to 26.

FIG. 24 is a plan view schematically illustrating a configurationexample of a logic substrate 601 configured to avoid interferencebetween a wire in the inter-circuit wiring layer and amoisture-resistant ring.

The logic substrate 601 is different from the above-mentioned logicsubstrate 211 of FIG. 14 in that instead of the signal processingcircuits 241L and 241R, signal processing circuits 611L and 611R withthe same circuit pattern are provided across the scribe area 42.Moreover, an inter-circuit wiring layer that connects the signalprocessing circuits 611L and 611R electrically is formed in theuppermost layer of the logic substrate 601 as in the logic substrate211. In this example, wires 612-1 to 612-3 in the inter-circuit wiringlayer connect the signal processing circuits 611L and 611R electrically.

Furthermore, a moisture-resistant ring 613 is formed along the vicinityof an outer periphery of the logic substrate 601 in such a manner as tosurround an outer periphery of the signal processing circuits 611L and611R.

The structure of the moisture-resistant ring 613 is described here withreference to FIGS. 25 and 26. FIG. 25 is a cross-sectional viewschematically illustrating a cross section of the moisture-resistantring 613. FIG. 26 is a perspective view schematically illustrating partof the moisture-resistant ring 613.

The moisture-resistant ring 613 includes a wall 621 made of a materialof a contact, dummy wires 622-1 to 622-6, walls 623-1 to 623-5 made of amaterial of a via, a wall 624, and a dummy wire 625.

The dummy wires 622-1 to 622-6 and the dummy wire 625 are formedrespectively in different wiring layers of the logic substrate 601, andare dummy wires that are not used for the transmission of a signal. Inthis example, seven wiring layers of the logic substrate 601 are stackedon a substrate layer 631 including, for example, a silicon substrate. Inaddition, the dummy wires 622-1 is formed in the first wiring layer atthe bottom of the logic substrate 601. The dummy wires 622-2 to 622-6are formed in the second to sixth wiring layers of the logic substrate601. The dummy wire 625 is formed in the seventh wiring layer at the topof the logic substrate 601.

The dummy wires 622-1 to 622-6 and the dummy wire 625 have substantiallythe same rectangular ring shape. The dummy wires 622-1 to 622-6 and thedummy wire 625 are formed along the vicinity of the outer periphery ofthe logic substrate 601 in each wiring layer in such a manner as tosurround the outer periphery of the signal processing circuits 611L and611R.

The wall 621, the walls 623-1 to 623-5, and the wall 624 havesubstantially the same rectangular ring shape. The wall 621, the walls623-1 to 623-5, and the wall 624 are formed along the vicinity of theouter periphery of the logic substrate 601 in such a manner as tosurround the outer periphery of the signal processing circuits 611L and611R.

The wall 621 is formed in the same step as a contact that connects thesubstrate layer 631 and the first wiring layer to connect the substratelayer 631 and the dummy wire 622-1.

The walls 623-1 to 623-5 are formed in the same step as vias thatconnect adjacent wiring layers of the first to sixth wiring layers. Thewall 623-1 is a via that connects the dummy wire 622-1 and the dummywire 622-2. The wall 623-2 is a via that connects the dummy wire 622-2and the dummy wire 622-3. The wall 623-3 is a via that connects thedummy wire 622-3 and the dummy wire 622-4. The wall 623-4 is a via thatconnects the dummy wire 622-4 and the dummy wire 622-5. The wall 623-5is a via that connects the dummy wire 622-5 and the dummy wire 622-6.

The wall 624 is formed in the same step as a via that connects the sixthand seventh wiring layers. The wall 624 is a via that connects the dummywire 622-6 and the dummy wire 625.

For example, copper is used for the first to sixth wiring layers. Thewall 621 is made of tungsten. The dummy wires 622-1 to 622-6 and thewalls 623-1 to 623-5 are made of copper. Moreover, for example, aninsulating film made of a low-K material with a low dielectric contactis used for an inter-layer insulating film 632 from a surface of thesubstrate layer 631 to an upper end of the sixth wiring layer. Inaddition, the first to sixth wiring layers are used for, for example,the transmission of a high-speed signal.

On the other hand, for example, aluminum is used for the seventh wiringlayer. The dummy wire 625 is made of aluminum. Moreover, the wall 624 ismade of, for example, tungsten. Furthermore, for example, a highlywater-resistant oxide film with a higher dielectric constant than theinter-layer insulating film 632 (for example, an oxide silicon film) isused for an inter-layer insulating film 633 above the upper end of thesixth wiring layer. In addition, the seventh wiring layer is used for,for example, the transmission of a low-speed signal of a power supply orthe like. Moreover, the seventh wiring layer serves as the inter-circuitwiring layer.

In this manner, the moisture-resistant ring 613 forms a wall thatsurrounds the periphery of the logic substrate 601 with the wall 621 tothe dummy wire 625, and prevents moisture from entering the signalprocessing circuits 611L and 611R from a side surface of the logicsubstrate 601.

Moreover, the moisture-resistant ring 613 is not provided between thesignal processing circuits 611L and 611R. Therefore, the wires 612-1 to612-3 that connect the signal processing circuits 611L and 611R do notinterfere with the moisture-resistant ring 613.

Incidentally, the circumference of the moisture-resistant ring 613 issubstantially the same as that of the pixel circuit 21, and is largerthan the exposure field of the exposure apparatus. Therefore, when thelayers above the substrate layer 631 of the logic substrate 601 (thelayers including the moisture-resistant ring 613) are formed, splitexposure is used.

Moreover, the moisture-resistant ring 613 is not necessarily required tobe formed in such a manner as to surround the entire periphery of thelogic substrate 601. The moisture-resistant ring 613 may be formed insuch a manner as to surround, for example, only part of the periphery ofthe logic substrate 601 within a range that can ensure moistureresistance.

Furthermore, also if, for example, three or more signal processingcircuits are placed in the logic substrate, it is similarly required toform the moisture resistant-ring in such a manner as to contain all thesignal processing circuits within it and surround the periphery or partof the periphery of the logic substrate.

Next, a second method for avoiding interference between a wire in theinter-circuit wiring layer and a moisture-resistant ring is describedwith reference to FIGS. 27 to 33.

FIG. 27 is a plan view schematically illustrating a configurationexample of a logic substrate 651 configured to avoid interferencebetween a wire in the inter-circuit wiring layer and amoisture-resistant ring.

The logic substrate 651 is different from the above-mentioned logicsubstrate 601 of FIG. 24 in that, instead of the signal processingcircuits 611L and 611R, signal processing circuits 661L and 661R withthe same circuit pattern are provided across the scribe area 42.Moreover, an inter-circuit wiring layer that connects the signalprocessing circuits 661L and 661R electrically is formed in theuppermost layer of the logic substrate 651 as in the logic substrate601. In this example, wires 662-1 to 662-3 in the inter-circuit wiringlayer connect the signal processing circuits 661L and 661R electrically.

Furthermore, the logic substrate 651 is different from the logicsubstrate 601 in that, instead of the moisture-resistant ring 613,moisture-resistant rings 663L to 663R are formed. The moisture-resistantring 663L is formed along the vicinity of an outer periphery of thesignal processing circuit 661L in such a manner as to surround theperiphery of the signal processing circuit 661L. The moisture-resistantring 663R is formed along the vicinity of an outer periphery of thesignal processing circuit 661R in such a manner as to surround theperiphery of the signal processing circuit 661R.

The structure of the moisture-resistant ring 663R is described here withreference to FIGS. 28 to 33. Incidentally, although not described indetail, the moisture-resistant ring 663L also has substantially the samestructure as the moisture-resistant ring 663R. Moreover, a referencesign of a portion of the moisture-resistant ring 663L corresponding toeach portion of the moisture-resistant ring 663R is expressed by areference sign having the letter “L” replaced with “R” included in thereference sign of each portion of the moisture-resistant ring 663Rbelow.

FIG. 28 is a cross-sectional view schematically illustrating a crosssection of a portion other than areas A1R-1 to A1R-3 and areas A2R-1 toA2R-3 of the moisture-resistant ring 663R. FIG. 29 is a perspective viewschematically illustrating part of the portion other than the areasA1R-1 to A1R-3 and the areas A2R-1 to A2R-3 of the moisture-resistantring 663R.

FIG. 30 is a cross-sectional view schematically illustrating a crosssection of a portion where the wire 662-1 passes in the area A1L-1 ofthe moisture-resistant ring 663L and the area A1R-1 of themoisture-resistant ring 663R. FIG. 31 is a perspective viewschematically illustrating the vicinity of the area A1R-1 of themoisture-resistant ring 663R.

FIG. 32 is a cross-sectional view schematically illustrating a crosssection at the same position in the area A2R-1 of the moisture-resistantring 663R as the portion where the wire 662-1 passes in the area A1L-1of the moisture-resistant ring 663L. FIG. 33 is a perspective viewschematically illustrating the vicinity of the area A2R-1 of themoisture-resistant ring 663R. Incidentally, in FIG. 33, only a dummywire 675R in the uppermost layer is made see-through.

The moisture-resistant ring 663R includes a wall 671R, dummy wires672R-1 to 672R-6, walls 673R-1 to 673R-5, a wall 674R, and the dummywire 675R. The moisture-resistant ring 663R has substantially the samestructure as the moisture-resistant ring 613 described above withreference to FIGS. 25 and 26. In other words, the moisture-resistantring 663R similarly has the seven-layer stacked structure as in themoisture-resistant ring 613 and also is made of the same material as themoisture-resistant ring 613.

For example, an insulating film made of a low-K material is used for aninter-layer insulating film 682 from a surface of a substrate layer 681to an upper end of the sixth wiring layer as in the inter-layerinsulating film 632 of the logic substrate 601. Moreover, for example,an oxide film (for example, an oxide silicon film) is used for aninter-layer insulating film 683 above the upper end of the sixth wiringlayer as in the inter-layer insulating film 633 of the logic substrate601.

However, the moisture-resistant ring 663 R is different from themoisture-resistant ring 613 in that parts of the wall 674R and the dummywire 675R are not formed and are discontinuous. Specifically, the wall674R and the dummy wire 675R are discontinuous in portions where thewires 662-1 to 662-3 in the areas A1R-1 to A1R-3 on the left side of themoisture-resistant ring 663R pass.

For example, as illustrated in FIGS. 30 and 31, the wall 674R and thedummy wire 675R are discontinuous in the portion where the wire 662-1 inthe area A1R-1 passes to prevent interference with the wire 662-1.Moreover, although illustration is omitted, the wall 674R and the dummywire 675R are also discontinuous in the portion where the wire 662-2 inthe area A1R-2 passes and the portion where the wire 662-3 in the areaA1R-3 passes to prevent interference with the wires 662-2 and 662-3.

Similarly, a wall 674L and a dummy wire 675L of the moisture-resistantring 663L are also discontinuous in portions where the wires 662-1 to662-3 in the areas A1L-1 to A1L-3 on the right side of themoisture-resistant ring 663L pass to prevent interference with the wires662-1 to 662-3.

Moreover, the wall 674R of the moisture-resistant ring 663R isdiscontinuous in portions corresponding to the discontinuous portions ofthe wall 674L in the areas A1L-1 to A1L-3 of the moisture-resistant ring663L. For example, the wall 674R is discontinuous at the same portion asthe discontinuous portion of the wall 674L in the area A1L-1 on theright side of the moisture-resistant ring 663L, in the area A2R-1 on theright side of the moisture-resistant ring 663R as illustrated in FIGS.32 and 33. Moreover, although illustration is omitted, the wall 674R isdiscontinuous at the same portions as the discontinuous portions of thewall 674L in the areas A1L-2 and A1L-3 on the right side of themoisture-resistant ring 663L, in the areas A2R-2 and A2R-3 on the rightside of the moisture-resistant ring 663R.

Similarly, the wall 674L of the moisture-resistant ring 663L isdiscontinuous at portions corresponding to the discontinuous portions ofthe wall 674R in the areas A1R-1 to A1R-3 of the moisture-resistant ring663R.

Consequently, the discontinuous portions of the wall 674L of themoisture-resistant ring 663L are the same as the discontinuous portionsof the wall 674R of the moisture-resistant ring 663R. Accordingly, thewalls 674R and 674L have the same and left-right symmetric shape.

Incidentally, the dummy wire 675R is unbroken and continuous in theareas A2R-1 to A2R-3. Similarly, the dummy wire 675L is unbroken andcontinuous in the areas A2L-1 to A2L-3.

As described above, the moisture-resistant ring 663R forms a wallsurrounding the periphery of the signal processing circuit 661R with thewall 671R to the dummy wire 675R, and prevents moisture from enteringthe signal processing circuit 661R from a side surface of the logicsubstrate 651. Similarly, the moisture-resistant ring 663L forms a wallsurrounding the periphery of the signal processing circuit 661L with awall 671L to the dummy wire 675L, and prevents moisture from enteringthe signal processing circuit 661L from a side surface of the logicsubstrate 651.

Moreover, as described above, the moisture-resistant rings 663L and 663Rdo not interfere with the wires 662-1 to 662-3 connecting the signalprocessing circuits 661L and 661R.

Furthermore, the discontinuous section of the wall 674R and the dummywire 675R of the moisture-resistant ring 663R is very short. The waterresistance of the inter-layer insulating film 683 is also high.Accordingly, the moisture resistance of the moisture-resistant ring 663Ris hardly reduced. Similarly, the discontinuous section of the wall 674Land the dummy wire 675L of the moisture-resistant ring 663L is veryshort. The water resistance of the inter-layer insulating film 683 isalso high. Accordingly, the moisture resistance of themoisture-resistant ring 663L is hardly reduced.

Moreover, the wall 674L of the moisture-resistant ring 663L and the wall674R of the moisture-resistant ring 663R have the same shape.Accordingly, it is possible to, for example, use the same photomask forexposure and achieve cost reduction.

Incidentally, the moisture-resistant rings 663L and 663R are notnecessarily required to be formed in such a manner as to surround theentire peripheries of the signal processing circuits 661L and 661R,respectively, and for example, may surround only parts of theperipheries within a range that can ensure moisture resistance.

Moreover, the discontinuous portions of the walls 674L and 674R otherthan the portions where the wires 662-1 to 662-3 pass are notnecessarily required to be provided. However, the walls 674L and 674R donot have the same shape without the discontinuous portions. Accordingly,there arises a need to use split exposure.

Furthermore, also if, for example, three or more signal processingcircuits are placed in the logic circuit, the moisture-resistant ring ofeach signal processing circuit can be formed by a similar method in sucha manner as to avoid interference with wires connecting the signalprocessing circuits.

(Method for Manufacturing the Moisture-Resistant Rings 663L and 663R)

Next, a method for manufacturing the moisture-resistant rings 663L and663R of the logic substrate 651 is described with reference to FIGS. 34to 40.

Incidentally, a left diagram in each of FIGS. 34 to 40 schematicallyillustrates a cross section of a portion where the wires 662-1 to 662-3do not pass, in a portion where the right side of the moisture-resistantring 663L and the left side of the moisture-resistant ring 663R areadjacent. On the other hand, a right diagram in each of FIGS. 34 to 40schematically illustrates a cross section of a portion where the wire662-1 passes, in a portion where the right side of themoisture-resistant ring 663L and the left side of the moisture-resistantring 663R are adjacent.

Moreover, the step of forming a portion above the inter-layer insulatingfilm 682 with the already formed wall 671L to a dummy wire 672L-6 of themoisture-resistant ring 663L and the wall 671R to the dummy wire 672R-6of the moisture-resistant ring 663R, and the inter-layer insulating film682 is described below. Incidentally, one-shot exposure is used forexposure in the previous steps.

Firstly, as illustrated in FIG. 34, an oxide film 691 is deposited onthe inter-layer insulating film 682.

Next, as illustrated in FIG. 35, the oxide film 691 is etched to formgrooves 692L and 692R. The groove 692L is formed in such a manner as tobe substantially superposed on a wall 673L-5 via the dummy wire 672L-6when viewed from above. However, the groove 692L is for forming the wall674L of the moisture-resistant ring 663L, and is not formed at theabove-mentioned portions where the wall 674L is discontinuous.Similarly, the groove 692R is formed in such a manner as to besubstantially superposed on the wall 673R-5 via the dummy wire 672R-6when viewed from above. However, the groove 692R is for forming the wall674R of the moisture-resistant ring 663R and is not formed at theabove-mentioned portions where the wall 674R is discontinuous.

Moreover, as described above, the walls 674L and 674R have the sameshape. Accordingly, the grooves 692L and 692R have the same shape.Therefore, the grooves 692L and 692R can be formed by one-shot exposureusing the same photomask.

Next, as illustrated in FIG. 36, a metal film 693 made of tungsten isevaporated onto the oxide film 691. At this point in time, the metalfilm 693 is evaporated thick in such a manner as to bury the grooves692L and 692R completely.

Next, as illustrated in FIG. 37, the metal film 693 on the oxide film691 is removed by polishing, leaving the metal film 693 in the grooves692L and 692R. Consequently, the walls 674L and 674R made of tungstenare formed.

Next, as illustrated in FIG. 38, a metal film 694 made of aluminum isevaporated onto the oxide film 691.

Next, as illustrated in FIG. 39, the metal film 694 is etched.Consequently, the inter-circuit wiring layer including the wires 662-1to 662-3 and the dummy wires 675L and 675R is formed. Split exposure isused to form the inter-circuit wiring layer as described above.

Lastly, as illustrated in FIG. 40, an oxide film is deposited on theinter-circuit wiring layer. Consequently, the inter-layer insulatingfilm 683 is formed, together with the oxide film 691 deposited in thestep described above with reference to FIG. 34. Incidentally, forexample, a protective layer made of polyimide or the like is furtherformed on the inter-layer insulating film.

Next, a third method for avoiding interference between a wire in theinter-circuit wiring layer and a moisture-resistant ring is describedwith reference to FIGS. 41 to 71.

In the example described above with reference to FIGS. 27 to 33, almostall the wiring layers of the logic substrate 651 can be formed byone-shot exposure. Accordingly, cost reduction can be achieved. On theother hand, the inter-circuit wiring layer is limited to be theuppermost layer of the logic substrate 651 and also the number ofdiscontinuous sections of the moisture-resistant rings 663L and 663Rcannot be very much increased, considering moisture resistance.Therefore, complicated wiring cannot be very much achieved between twosignal processing circuits.

Hence, in order to achieve cost reduction and achieve more complicatedwiring between signal processing circuits while ensuring moistureresistance, for example, a combination of the above-mentioned first andsecond methods is conceivable. In other words, it is conceivable tocombine a moisture-resistant ring surrounding the periphery of eachsignal processing circuit (hereinafter also referred to as the circuitmoisture-resistant ring), and a moisture-resistant ring surrounding theperiphery of the logic substrate (hereinafter also referred to as thesubstrate moisture-resistant ring).

FIG. 41 is a plan view schematically illustrating a configurationexample of a moisture-resistant ring of a logic substrate 701 in acombination of the circuit moisture-resistant rings and the substratemoisture-resistant ring.

The logic substrate 701 is different from the above-mentioned logicsubstrate 601 of FIG. 24 in that instead of the signal processingcircuits 611L and 611R, signal processing circuit 711L and 711R areprovided across the scribe area 42. Moreover, there is also a differencein that a moisture-resistant ring 712L surrounding the periphery of thesignal processing circuit 711L and a moisture-resistant ring 712Rsurrounding the periphery of the signal processing circuit 711R areformed, and in a layer above them, a moisture-resistant ring 713surrounding an outer periphery of the signal processing circuits 711Land 711R is further formed along the vicinity of an outer periphery ofthe logic substrate 701.

In this manner, the logic substrate 701 has a dual-layer structure wherethe moisture-resistant rings 712L and 712R that are the circuitmoisture-resistant rings, and the moisture-resistant ring 713 being thesubstrate moisture-resistant ring are stacked.

Incidentally, in the following description, the lower side of FIG. 41 isassumed to be the front of the logic substrate 701, the upper side ofFIG. 41 to be the back of the logic substrate 701, the left-hand side ofFIG. 41 to be the left-hand side of the logic substrate 701, and theright-hand side of FIG. 41 to be the right-hand side of the logicsubstrate 701. Therefore, a direction in which the scribe area 42extends is the front-and-back direction (or depth direction) of thelogic substrate 701, and a direction in which the signal processingcircuits 711L and 711R are adjacent is the left-and-right direction (orlateral direction) of the logic substrate 701.

Here, a first embodiment of the moisture-resistant ring with thedual-layer structure is described with reference to FIGS. 42 to 44. Inthe first embodiment, the moisture-resistant ring with the dual-layerstructure includes a moisture-resistant ring 712La, a moisture-resistantring 712Ra, and a moisture-resistant ring 713 a.

FIG. 42 is an image diagram schematically illustrating dummy wiresforming the moisture-resistant ring 712La, the moisture-resistant ring712Ra, and the moisture-resistant ring 713 a. The moisture-resistantring 712La is configured including substantially the same rectangularring-shaped dummy wires 721L-1 to 721L-3. The moisture-resistant ring712Ra is configured including substantially the same rectangularring-shaped dummy wires 721R-1 to 721R-3. The moisture-resistant ring713 a is configured including substantially the same rectangularring-shaped dummy wires 722-1 to 722-3.

FIG. 43 is a perspective view schematically illustrating theconfiguration of the moisture-resistant ring in the vicinity enclosed ina frame C1 of FIG. 41. FIG. 44 is a diagram of FIG. 43 excluding themoisture-resistant ring 713 a.

The moisture-resistant ring 712La includes the dummy wires 721L-1 to721L-3, a wall 723L made of a material of a contact, and walls 724L-1 to724L-3 made of a material of a via. The moisture-resistant ring 712Raincludes the dummy wires 721R-1 to 721R-3, a wall 723R made of thematerial of a contact, and walls 724R-1 to 724R-3 made of the materialof a via. The moisture-resistant ring 713 a includes the dummy wires722-1 to 722-3, and walls 725-1 and 725-2 made of the material of a via.

The dummy wires 721L-1 and 721R-1 are formed in the lowermost firstwiring layer of the logic substrate 701. The dummy wires 721L-2 and721R-2 are formed in a second wiring layer of the logic substrate 701.The dummy wires 721L-3 and 721R-3 are formed in a third wiring layer ofthe logic substrate 701. The dummy wire 722-1 is formed in a fourthwiring layer of the logic substrate 701. The dummy wire 722-2 is formedin a fifth wiring layer of the logic substrate 701. The dummy wire 722-3is formed in the uppermost sixth wiring layer of the logic substrate701.

The dummy wires 721L-1 to 721L-3 have substantially the same rectangularring shape, and are formed along the vicinity of an outer periphery ofthe signal processing circuit 711L in each wiring layer in such a manneras to surround the periphery of the signal processing circuit 711L.

The wall 723L and the walls 724L-1 to 724L-3 have substantially the samerectangular ring shape, and are formed along the vicinity of the outerperiphery of the signal processing circuit 711L in such a manner as tosurround the periphery of the signal processing circuit 711L. The wall723L is formed in the same step as a contact that connects a substratelayer 751 (FIG. 47 and the like) and the first wiring layer of the logicsubstrate 701 to connect the substrate layer 751 and the dummy wire721L-1. The walls 724L-1 to 724L-3 are formed in the same step as viasthat connect adjacent wiring layers of the first to fourth wiringlayers. The wall 724L-1 is the via that connects the dummy wires 721L-1and 721L-2. The wall 724L-2 is the via that connects the dummy wires721L-2 and 721L-3. The wall 724L-3 is the via that connects the dummywires 721L-3 and 722-1.

In this manner, the moisture-resistant ring 712La forms a wall thatsurrounds the periphery of the signal processing circuit 711L with thewall 723L to the wall 724L-3.

The dummy wires 721R-1 to 721R-3 have substantially the same rectangularring shape, and are formed along the vicinity of an outer periphery ofthe signal processing circuit 711R in each wiring layer in such a manneras to surround the periphery of the signal processing circuit 711R.

The wall 723R and the walls 724R-1 to 724R-3 have substantially the samerectangular ring shape, and are formed along the vicinity of the outerperiphery of the signal processing circuit 711R in such a manner as tosurround the periphery of the signal processing circuit 711R. The wall723R is formed in the same step as a contact that connects the substratelayer 751 (FIG. 47 and the like) and the first wiring layer of the logicsubstrate 701 to connect the substrate layer 751 and the dummy wire721R-1. The walls 724R-1 to 724R-3 are formed in the same step as viasthat connect adjacent wiring layers of the first to fourth wiringlayers. The wall 724R-1 is a via that connects the dummy wires 721R-1and 721R-2. The wall 724R-2 is a via that connects the dummy wires721R-2 and 721R-3. The wall 724R-3 is a via that connects the dummywires 721R-3 and 722-1.

In this manner, the moisture-resistant ring 712Ra forms a wall thatsurrounds the periphery of the signal processing circuit 711R with thewall 723R to the wall 724R-3.

The dummy wires 722-1 to 722-3 have substantially the same rectangularring shape, and are formed along the vicinity of the outer periphery ofthe logic substrate 701 in each wiring layer in such a manner as tosurround the outer periphery of the signal processing circuits 711L and711R.

The walls 725-1 and 725-2 have substantially the same rectangular ringshape, and are formed along the vicinity of the outer periphery of thelogic substrate 701 in such manner as to surround the outer periphery ofthe signal processing circuits 711L and 711R. The walls 725-1 and 725-2are formed in the same step as vias that connect adjacent wiring layersof the fourth to sixth wiring layers. The wall 725-1 is a via thatconnects the dummy wires 722-1 and 722-2. The wall 725-2 is a via thatconnects the dummy wires 722-2 and 722-3.

In this manner, the moisture-resistant ring 713 a forms a wall thatsurrounds the periphery of the logic substrate 701 with the dummy wires722-1 to 722-3.

One-shot exposure is used to form the layers below the layer includingthe walls 724L-3 and 724R-3. Split exposure is used to form the layersabove the layer including the dummy wire 722-1. Consequently, the costcan be reduced more than a case where split exposure is used to form allthe layers, as described above with reference to FIGS. 24 to 26.

Moreover, for example, copper is used for the first to sixth wiringlayers. In addition, the dummy wires 721L-1 to 721L-3, 721R-1 to 721R-3,and 722-1 to 722-3, and the walls 724L-1 to 724L-3, 724R-1 to 724R-3,725-1, and 725-2 are made of copper. The walls 723L and 723R are made oftungsten. Moreover, for example, an insulating film made of a low-Kmaterial with a low dielectric constant is used for an inter-layerinsulating film from a surface of the substrate layer 751 to an upperend of the sixth wiring layer.

In addition, for example, an inter-circuit wiring layer that connectsthe signal processing circuits 711L and 711R is provided in the samelayers as the dummy wires 722-1 to 722-3. Accordingly, more complicatedwiring can be achieved between the two signal processing circuits.

However, as illustrated in FIG. 43, if the moisture-resistant rings712La and 712Ra and the moisture-resistant ring 713 a are simplystacked, moisture enters the wiring layers and the signal processingcircuits 711L and 711R of the logic substrate 701; accordingly, moistureresistance cannot be ensured.

For example, as indicated by an arrow of FIG. 43, moisture that hasentered from the space between the moisture-resistant rings 712La and712Ra on the side surfaces of the logic substrate 701 in areas enclosedin the frame C1 and a frame C2 of FIG. 41 proceeds upward in FIG. 43,and enters the inside of the moisture-resistant ring 713 a. Furthermore,the moisture enters the inside of the moisture-resistant ring 712La andthe inside of the moisture-resistant ring 712Ra over themoisture-resistant rings 712La and 712Ra.

Therefore, it is required to block these moisture entry paths andimprove moisture resistance.

A second embodiment of the moisture-resistant ring with the dual-layerstructure is described here with reference to FIGS. 45 to 48. The secondembodiment is different in the improvement of moisture resistance fromthe first embodiment. Incidentally, the same reference signs areassigned to portions corresponding to FIGS. 43 and 44, in FIGS. 45 to48.

FIG. 45 is a perspective view schematically illustrating theconfiguration of the moisture-resistant ring in the vicinity enclosed inthe frame C1 of FIG. 41. FIG. 46 is a diagram of FIG. 44 excluding aportion above the wall 725-1. FIG. 47 is a cross-sectional view of anA-A part of FIG. 41. FIG. 48 is a cross-sectional view of a B-B part ofFIG. 41.

FIG. 45 is different from FIG. 43 in that instead of the dummy wire722-1, a dummy wire 741 is provided in the fourth wiring layer. Inaddition, the moisture-resistant ring with the dual-layer structureincludes a moisture-resistant ring 712Lb, a moisture-resistant ring712Rb, and a moisture-resistant ring 713 b.

The moisture-resistant ring 712Lb includes the dummy wires 721L-1 to721L-3, the wall 723L, the walls 724L-1 to 724L-3, and part of the dummywire 741. The moisture-resistant ring 712Rb includes the dummy wires721R-1 to 721R-3, the wall 723R, the walls 724R-1 to 724R-3, and part ofthe dummy wire 741. The moisture-resistant ring 713 b includes the dummywires 722-2 and 722-3, the walls 725-1 and 725-2, and part of the dummywire 741. The dummy wire 741 is located at the boundary between themoisture-resistant rings 712Lb and 712Rb and the moisture-resistant ring713 b, and is included as a component of each moisture-resistant ring.

Incidentally, the dummy wire 741 is described below, separated into aring portion 741A and a lid portion 741B by an auxiliary line indicatedby a dotted line of FIG. 46, as appropriate.

The ring portion 741A of the dummy wire 741 has the same shape as thedummy wire 722-1 of FIG. 43. Therefore, the dummy wire 741 has the shapeof the dummy wire 722-1 with the addition of the lid portion 741B.

The lid portion 741B has a rectangular plate shape extending in thefront-and-back direction, and connects the front and back sides of thering portion 741A. The left side surface of the lid portion 741B is atsubstantially the same position as the left side surface of the rightside of the dummy wire 721L-3 in the left-and-right direction. The rightside surface of the lid portion 741B is at substantially the sameposition as the right side surface of the left side of the dummy wire721R-3 in the left-and-right direction.

Therefore, a barrier unit including the partial ring portion 741A andthe lid portion 741B of the dummy wire 741 blocks an upper surface of anarea between the moisture-resistant rings 712Lb and 712Rb. In otherwords, the barrier unit separates the area between themoisture-resistant rings 712Lb and 712Rb and an area surrounded by themoisture-resistant ring 713 b. Consequently, as illustrated in FIGS. 47and 48, the moisture-resistant ring 712Lb, the moisture-resistant ring712Rb, and the moisture-resistant ring 713 b ensure the separation of anon-moisture resistant area 752 and a moisture-resistant area 753.

Incidentally, the non-moisture resistant area 752 is an area that is notsurrounded by any of the moisture-resistant rings 712Lb, 712Rb, and 713b on the substrate layer 751. The moisture-resistant area 753 is an areasurrounded by at least one of the moisture-resistant rings 712Lb, 712Rb,and 713 b on the substrate layer 751. Circuits, wires, and the like areprovided in the moisture-resistant area 753; accordingly, moistureresistance is required.

In addition, also if, for example, an insulating film made of a low-Kmaterial is used for the inter-layer insulating film from the surface ofthe substrate layer 751 to the upper end of the sixth wiring layer,including the layers adjacent to the layer including the barrier unit,moisture that has entered the non-moisture resistant area 752 isprevented from entering the moisture-resistant area 753. Therefore, themoisture resistance of the moisture-resistant area 753 is retained, andthe reliability of a solid state imaging device using the logicsubstrate 701 improves.

Moreover, as compared to the above-mentioned technology disclosed inPatent Document 3, there is no need to provide a moisture-resistant filmdedicated to ensure moisture resistance. Accordingly, it is possible toreduce the manufacturing process and reduce the manufacturing cost.

Incidentally, split exposure is used to form the fourth wiring layerincluding the dummy wire 741.

Next, a third embodiment of the moisture-resistant ring with thedual-layer structure is described with reference to FIGS. 49 to 54. Thethird embodiment is for improving moisture resistant as in the secondembodiment. Incidentally, the same reference signs are as signed toportions corresponding to FIGS. 43 and 44, in FIGS. 49 to 54.

FIG. 49 is a perspective view schematically illustrating theconfiguration of the moisture-resistant ring in the vicinity enclosed inthe frame C1 of FIG. 41. FIG. 50 is a diagram of FIG. 49 excluding aportion above a wall 762. FIG. 51 is a diagram of FIG. 50 with theaddition of the wall 762. FIG. 52 is a diagram of FIG. 51 with theaddition of a dummy wire 763. FIG. 53 is a cross-sectional view of theA-A part of FIG. 41. FIG. 54 is a cross-sectional view of the B-B partof FIG. 41.

FIG. 49 is different from FIG. 43 in the configuration from the third tofourth wiring layers. Specifically, instead of the dummy wires 721L-3and the dummy wire 721R-3, a dummy wire 761 is provided in the thirdwiring layer. Instead of the walls 724L-3 and 724R-3, the wall 762 isprovided between the third and fourth wiring layers. Instead of thedummy wire 722-1, the dummy wire 763 is provided in the fourth wiringlayer. In addition, the moisture-resistant ring with the dual-layerstructure includes moisture-resistant rings 712Lc, 712Rc, and 713 c.

The moisture-resistant ring 712Lc includes the dummy wires 721L-1 and721L-2, the wall 723L, the walls 724L-1 and 724L-2, part of the dummywire 761, part of the wall 762, and part of the dummy wire 763. Themoisture-resistant ring 712Rc includes the dummy wires 721R-1 and721R-2, the wall 723R, the walls 724R-1 and 724R-2, part of the dummywire 761, part of the wall 762, and part of the dummy wire 763. Themoisture-resistant ring 713 c includes the dummy wires 722-2 and 722-3,the walls 725-1 and 725-2, part of the dummy wire 761, part of the wall762, and part of the dummy wire 763. The dummy wire 761, the wall 762,and the dummy wire 763 are located at the boundary between themoisture-resistant rings 712Lc and 712Rc and the moisture-resistant ring713 c, and are included as components of each moisture-resistant ring.

Incidentally, the dummy wire 761 is described below, separated into aring portion 761AL, a ring portion 761AR, a connection portion 761B-1, aconnection portion 761B-2 (not illustrated), a lid portion 761C-1, and alid portion 761C-2 by auxiliary lines indicated by dotted lines of FIG.50, as appropriate. Moreover, the wall 762 is described below, separatedinto a ring portion 762AL, a ring portion 762AR, a connection portion762B-1, a connection portion 762B-2 (not illustrated), and connectionportions 762C-1 to 762C-4 by an auxiliary line indicated by a dottedline of FIG. 51, as appropriate. Furthermore, the dummy wire 763 isdescribed below, separated into a ring portion 763A and lid portions763B-1 to 763B-3 by an auxiliary line indicated by a dotted line of FIG.52, as appropriate.

The ring portions 761AL and 761AR of the dummy wire 761 have the sameshape as the dummy wires 721L-3 and 721R-3 of FIG. 43. Therefore, thedummy wire 761 has a shape where the connection portion 761B-1, theconnection portion 761B-2, the lid portion 761C-1, and the lid portion761C-2 are added to the dummy wires 721L-3 and 721R-3.

The connection portion 761B-1 connects the front side of the ringportion 761AL and the front side of the ring portion 761AR. Theunillustrated connection portion 761B-2 connects the back side of thering portion 761AL and the back side of the ring portion 761AR.Therefore, the sides of the ring portion 761AL excluding the right side,the sides of the ring portion 761AR excluding the left side, theconnection portion 761B-1, and the connection portion 761B-2 form a ringthat surrounds the outer periphery of the signal processing circuits711L and 711R along the vicinity of the outer periphery of the logicsubstrate 701.

The lid portions 761C-1 and 761C-2 have a rectangular plate shapeextending in the front-and-back direction, and connect the connectionportions 761B-1 and 761B-2. The lid portions 761C-1 and 761C-2 areplaced at predetermined spacings between the right side of the ringportion 761AL and the left side of the ring portion 761AR.

A rectangular opening portion 761D-1 is then formed between the rightside of the ring portion 761AL and the lid portion 761C-1. A rectangularopening portion 761D-2 is formed between the lid portions 761C-1 and761C-2. A rectangular opening portion 761D-3 is formed between the lidportion 761C-2 and the left side of the ring portion 761AR. The openingportions 761D-1 to 761D-3 are of substantially the same size.

The wall 762 is a via that connects the dummy wires 761 and 763. Thering portions 762AL and 761AR of the wall 762 have the same shape as thewalls 724L-3 and 724R-3 of FIG. 43. Therefore, the wall 762 has a shapewhere the connection portions 762B-1, 762B-2, and 762C-1 to 762C-4 areadded to the walls 724L-3 and 724R-3.

The connection portion 762B-1 connects the front side of the ringportion 762AL and the front side of the ring portion 762AR on an uppersurface of the connection portion 761B-1 of the dummy wire 761. Theunillustrated connection portion 762B-2 connects the back side of thering portion 762AL and the back side of the ring portion 762AR on anupper surface of the connection portion 761B-2 (not illustrated) of thedummy wire 761. Therefore, the sides of the ring portion 762AL excludingthe right side, the sides of the ring portion 762AR excluding the leftside, the connection portion 762B-1, and the connection portion 762B-2form a ring that surrounds the outer periphery of the signal processingcircuits 711L and 711R along the vicinity of the outer periphery of thelogic substrate 701.

The connection portions 762C-1 to 762C-4 have a rectangular plate shapeextending in the front-and-back direction, and connect the connectionportions 762B-1 and 762B-2. The connection portions 761C-1 to 761C-4 areplaced at predetermined spacings between the right side of the ringportion 762AL and the left side of the ring portion 762AR. Theconnection portion 762C-1 is placed near the left end of an uppersurface of the lid portion 761C-1 of the dummy wire 761. The connectionportion 762C-2 is placed near the right end of the upper surface of thelid portion 761C-1 of the dummy wire 761. The connection portion 762C-3is placed near the left end of an upper surface of the lid portion761C-2 of the dummy wire 761. The connection portion 762C-4 is placednear the right end of the upper surface of the lid portion 761C-2 of thedummy wire 761.

Then, the ring portion 762AL, the connection portion 762B-1, theconnection portion 762C-1, and the connection portion 762B-2 (notillustrated) form an opening portion 762D-1 in such a manner as tosurround the periphery of the opening portion 761D-1 of the dummy wire761. The connection portion 762C-2, the connection portion 762B-1, theconnection portion 762C-3, and the connection portion 762B-2 (notillustrated) form an opening portion 762D-2 in such a manner as tosurround the periphery of the opening portion 761D-2 of the dummy wire761. The connection portion 762C-4, the connection portion 762B-1, thering portion 762AR, and the connection portion 762B-2 (not illustrated)form an opening portion 762D-3 in such a manner as to surround theperiphery of the opening portion 761D-3 of the dummy wire 761.

The ring portion 763A of the dummy wire 763 has the same shape as thedummy wire 722-1 of FIG. 43. Therefore, the dummy wire 763 has the shapeof the dummy wire 722-1 with the addition of the lid portions 763B-1 to763B-3.

The lid portions 763B-1 to 763B-3 have a plate shape extending in thefront-and-back direction, and connect the front side and the back sideof the ring portion 763A.

The left side surface of the lid portion 763B-1 is located leftward ofthe right side of the ring portion 762AL of the wall 762 in theleft-and-right direction, and is at substantially the same position asthe left side surface of the right side of the ring portion 761AL of thedummy wire 761. The right side surface of the lid portion 763B-1 islocated slightly rightward of the connection portion 762C-1 of the wall762 in the left-and-right direction. Therefore, the lid portion 763B-1blocks the opening portion 762D-1 of the wall 762 from above.

The left side surface of the lid portion 763B-2 is located slightlyleftward of the connection portion 762C-2 of the wall 762 in theleft-and-right direction. The right side surface of the lid portion763B-2 is located slightly rightward of the connection portion 762C-3 ofthe wall 762 in the left-and-right direction. Therefore, the lid portion763B-2 blocks the opening portion 762D-2 of the wall 762 from above.

The left side surface of the lid portion 763B-3 is located slightlyleftward of the connection portion 762C-4 of the wall 762 in theleft-and-right direction. The right side surface of the lid portion763B-3 is located slightly rightward of the left side of the ringportion 762AR of the wall 762 in the left-and-right direction, and is atsubstantially the same position as the right side surface of the leftside of the ring portion 761AR of the dummy wire 761. Therefore, the lidportion 763B-3 blocks the opening portion 762D-3 of the wall 762 fromabove.

A barrier unit including part of the dummy wire 761, part of the wall762, and part of the dummy wire 763 then blocks an upper surface of anarea between the moisture-resistant rings 712Lc and 712Rc. In otherwords, the barrier unit separates the area between themoisture-resistant rings 712Lc and 712Rc and an area surrounded by themoisture-resistant ring 713 c.

Consequently, as illustrated in FIGS. 53 and 54, the moisture-resistantrings 712Lc, 712Rc, and 713 c ensure the separation of a non-moistureresistant area 771 and a moisture-resistant area 772. Accordingly,moisture that has entered the non-moisture resistant area 771 isprevented from entering the moisture-resistant area 772. Therefore, themoisture resistance of the moisture-resistant area 772 is retained, andthe reliability of a solid state imaging device using the logicsubstrate 701 improves.

Moreover, as illustrated in FIG. 53, the dummy wires in the third wiringlayer and the dummy wires in the fourth wiring layer are alternatelyplaced in the left-and-right direction in the barrier unit. The barrierunit has a chain structure having a cross section of a rectangularwave-like shape. Consequently, the area of each dummy wire can be madesmaller than the above-mentioned lid portion 741B of the dummy wire 741of FIG. 46 to facilitate manufacturing.

Furthermore, as compared to the above-mentioned technology disclosed inPatent Document 3, there is no need to provide a moisture-resistant filmdedicated to ensure moisture resistance. Accordingly, it is possible toreduce the manufacturing process and reduce the manufacturing cost.

Incidentally, split exposure is used to from the third wiring layerincluding the dummy wire 761, a layer including the wall 762 between thethird and fourth wiring layers, and the fourth wiring layer includingthe dummy wire 763.

Moreover, the number of alternately repeated dummy wires in the thirdand fourth wiring layers in the left-and-right direction is not limitedto this example and can be set to any given number.

Furthermore, the barrier unit may be formed using three or more wiringlayers.

Next, a fourth embodiment of the moisture-resistant ring with thedual-layer structure is described with reference to FIGS. 55 to 60. Thefourth embodiment is for improving moisture resistance as in the secondand third embodiments. Incidentally, the same reference sings areassigned to portions corresponding to FIGS. 43 and 44, in FIGS. 55 to60.

FIG. 55 is a perspective view schematically illustrating theconfiguration of the moisture-resistant ring in the vicinity enclosed inthe frame C1 of FIG. 41. FIG. 56 is a diagram of FIG. 55 excluding awall 782, and a portion above walls 783-1 and 783-2. FIG. 57 is adiagram of FIG. 56 with the addition of the wall 782, and the walls783-1 and 783-2. FIG. 58 is a diagram of FIG. 57 with the addition of adummy wire 784, and dummy wires 785-1 and 785-2. FIG. 59 is across-sectional view of the A-A part of FIG. 41. FIG. 60 is across-sectional view of the B-B part of FIG. 41.

FIG. 55 is different from FIG. 43 in the configuration from the third tofourth wiring layers. Specifically, instead of the dummy wires 721L-3and 721R-3, a dummy wire 781 is provided in the third wiring layer.Instead of the walls 724L-3 and 724R-3, the wall 782 and walls 783-1 to783-n (the wall 783-3 and later are not illustrated) are providedbetween the third wiring layer and the fourth wiring layer. Instead ofthe dummy wire 722-1, the dummy wire 784 and dummy wires 785-1 to 785-n(the wall 785-3 and later are not illustrated) are provided in thefourth wiring layer. In addition, the moisture-resistant ring with thedual-layer structure includes a moisture-resistant ring 712Ld, amoisture-resistant ring 712Rd, and a moisture-resistant ring 713 d.

Incidentally, if there is no need to distinguish the walls 783-1 to783-n individually, they are simply referred to as the wall 783 below.If there is no need to distinguish the dummy wires 785-1 to 785-nindividually, they are simply referred to as the dummy wire 785 below.

The moisture-resistant ring 712Ld includes the dummy wires 721L-1 and721L-2, the wall 723L, the walls 724L-1 and 724L-2, part of the dummywire 781, part of the wall 782, parts of the walls 783-1 to 783-n, partof the dummy wire 784, and parts of the dummy wires 785-1 to 785-n. Themoisture-resistant ring 712Rd includes the dummy wires 721R-1 and721R-2, the wall 723R, the walls 724R-1 and 724R-2, part of the dummywire 781, part of the wall 782, parts of the walls 783-1 to 783-n, partof the dummy wire 784, and parts of the dummy wires 785-1 to 785-n. Themoisture-resistant ring 713 d includes the dummy wires 722-2 and 722-3,the walls 725-1 and 725-2, part of the dummy wire 781, part of the wall782, parts of the walls 783-1 to 783-n, part of the dummy wire 784, andparts of the dummy wires 785-1 to 785-n. The dummy wire 781, the wall782, the walls 783-1 to 783-n, the dummy wire 784, and the dummy wires785-1 to 785-n are placed at the boundary between the moisture-resistantrings 712Ld and 712Rd and the moisture-resistant ring 713 d, and areincluded as components of each moisture-resistant ring.

Incidentally, the dummy wire 781 is described below, separated into aring portion 781AL, a ring portion 781AR, and lid portions 781B-1 to781B-(n+1) (the lid portion 781B-3 and later are not illustrated) byauxiliary lines indicated by dotted lines of FIG. 56, as appropriate.Moreover, the dummy wire 784 is described below, separated into a ringportion 784A, a lid portion 784B-1, and a lid portion 784B-2 (notillustrated) by an auxiliary line indicated by a dotted line of FIG. 58.

The ring portions 781AL and 781AR of the dummy wire 781 have the sameshape as the dummy wires 721L-3 and 721R-3 of FIG. 43. Therefore, thedummy wire 781 has a shape where the lid portions 781B-1 to 781B-(n+1)are added to the dummy wires 721L-3 and 721R-3.

Incidentally, if there is no need to distinguish the lid portions 781B-1to 781B-(n+1) individually, they are simply referred to as the lidportion 781B below.

Each lid portion 781B has a rectangular plate shape extending in theleft-and-right direction, and connects the right side of the ringportion 781AL and the left side of the ring portion 781AR. Each lidportion 781B is placed at predetermined spacings in the front-and-backdirection. The right side of the ring portion 781AL, the left side ofthe ring portion 781AR, the adjacent lid portion 781B then formrectangular opening portions 781C-1 to 781C-n.

Incidentally, if there is no need to distinguish the opening portions781C-1 to 781C-n individually, they are simply referred to as theopening portion 781C below.

The wall 782 is a via that connects the dummy wires 781 and 784. Thewall 782 has a substantially rectangular ring shape, and is formed alongthe vicinity of the outer periphery of the logic substrate 701 in such amanner as to surround the outer periphery of the signal processingcircuits 711L and 711R. However, the wall 782 is recessed toward theinside of the logic substrate 701 in the vicinities enclosed in theframes C1 and C2 of FIG. 41 to match the shape of the dummy wire 781below the wall 782.

The walls 783-1 to 783-n are vias that connect the dummy wire 781 andthe dummy wires 785-1 to 785-n, respectively. The walls 783-1 to 783-nhave substantially the same rectangular ring shape, and are formed on anupper surface of the dummy wire 781 in such a manner as to respectivelysurround the peripheries of the openings 781C-1 to 781C-n of the dummywire 781.

The ring portion 784A of the dummy wire 784 has the same shape as thedummy wire 722-1 of FIG. 43. Therefore, the dummy wire 784 has the shapeof the dummy wire 722-1 with the addition of the lid portions 784B-1 and784B-2.

The lid portion 784B-1 has a rectangular plate shape extending in theleft-and-right direction. The lid portion 784B-1 blocks, from above, anopening portion formed by the ring portion 784A and the front recessedportion of the wall 782.

The lid portion 784B-2 (not illustrated) has a rectangular plate shapeextending in the left-and-right direction. The lid portion 784B-1blocks, from above, an opening portion formed by the ring portion 784Aand the back recessed portion (not illustrated) of the wall 782.

The dummy wires 785-1 to 785-n have a rectangular plate shape extendingin the left-and-right direction. The dummy wires 785-1 to 785-n areformed in such a manner as to respectively block the opening portions ofthe walls 783-1 to 783-n from above.

Therefore, a barrier unit including part of the dummy wire 781, part ofthe wall 782, the walls 783-1 to 783-n, part of the dummy wire 784, andthe dummy wires 785-1 to 785-n blocks an upper surface of an areabetween the moisture-resistant rings 712Ld and 712Rd. In other words,the barrier unit separates the area between the moisture-resistant rings712Ld and 712Rd and an area surrounded by the moisture-resistant ring713 d.

Consequently, as illustrated in FIGS. 59 and 60, the moisture-resistantring 712Ld, the moisture-resistant ring 712Rd, and themoisture-resistant ring 713 d ensure the separation of a non-moistureresistant area 791 and a moisture-resistant area 792. Accordingly,moisture that has entered the non-moisture resistant area 791 isprevented from entering the moisture-resistant area 792. Therefore, themoisture resistance of the moisture-resistant area 792 is retained, andthe reliability of a solid state imaging device using the logicsubstrate 701 improves.

Moreover, as illustrated in FIG. 60, the dummy wires in the third wiringlayer and the dummy wires in the fourth wiring layer are alternatelyplaced in the barrier unit in the front-and-back direction. The barrierunit has a chain structure having a cross section of a rectangularwave-like shape. Consequently, the area of each dummy wire can be madesmaller than the above-mentioned lid portion 741B of the dummy wire 741of FIG. 46 to facilitate manufacturing.

Furthermore, as compared to the above-mentioned technology disclosed inPatent Document 3, there is no need to provide a moisture-resistant filmdedicated to ensure moisture resistance. Accordingly, it is possible toreduce the manufacturing process and reduce the manufacturing cost.

Incidentally, split exposure is used to form the third wiring layerincluding the dummy wire 781, a layer between the third and fourthwiring layers including the wall 782 and the walls 783-1 to 783-n, andthe fourth wiring layer including the dummy wire 784 and the dummy wires785-1 to 785-n.

Moreover, the number of alternately repeated dummy wires in the thirdand fourth wiring layers in the front-and-back direction can be set toany given number.

Furthermore, the barrier unit may be formed using three or more wiringlayers.

FIGS. 61 to 63 illustrate a modification of the fourth embodiment of themoisture-resistant ring with the dual-layer structure. FIG. 61 is aperspective view schematically illustrating the configuration of themoisture-resistant ring in the vicinity enclosed in the frame C1 of FIG.41. FIG. 62 is a cross-sectional view of the A-A part of FIG. 41. FIG.63 is a cross-sectional view of the B-B part of FIG. 41.

In this modification, as illustrated in FIGS. 61 to 63, wires forconnecting the signal processing circuits 711L and 711R are provided inthe fourth wiring layer including the dummy wire 784 and the dummy wires785-1 to 785-n. For example, a wire 801-1 is provided between the dummywires 784 and 785-1. A wire 801-1 is provided between the dummy wires785-1 and 785-2.

In this manner, wires between the signal processing circuits 711L and711R can be provided effectively using a wiring layer forming thebarrier unit.

Next, a fifth embodiment of the moisture-resistant ring with thedual-layer structure is described with reference to FIGS. 64 to 68. Thefifth embodiment is for improving moisture resistance as in the secondto fourth embodiments. Incidentally, the same reference signs areassigned to portions corresponding to FIGS. 43 and 44, in FIGS. 64 to68.

FIG. 64 is a perspective view schematically illustrating theconfiguration of the moisture-resistant ring with the dual-layerstructure in the vicinity enclosed in the frame C1 of FIG. 41. FIG. 65is a diagram of FIG. 64 excluding a portion above a dummy wire 824. FIG.66 is a diagram of FIG. 65 with the addition of the dummy wire 824. FIG.67 is a cross-sectional view of the A-A part of FIG. 41. FIG. 68 is across-sectional view of the B-B part of FIG. 41.

FIG. 64 is different from FIG. 43 in the configuration from the first tofourth wiring layers. Specifically, dummy wires 822-1 to 822-3 are addedto the first to third wiring layers. A wall 821 is added between thesubstrate layer 751 and the first wiring layer. Walls 823-1 to 823-3 areadded between adjacent wiring layers of the first to fourth wiringlayers. Instead of the dummy wire 722-1, the dummy wire 824 is providedin the fourth wiring layer. In addition, the moisture-resistant ringwith the dual-layer structure includes moisture-resistant rings 712Le,712Re, 713 e, and 714.

The moisture-resistant ring 712Le includes the dummy wires 721L-1 to721L-3, the wall 723L, the walls 724L-1 to 724L-3, part of the dummywire 824. The moisture-resistant ring 712Re includes the dummy wires721R-1 to 721R-3, the wall 723R, the walls 724R-1 to 724R-3, and part ofthe dummy wire 824. The moisture-resistant ring 713 e includes the dummywires 722-2 and 722-3, the walls 725-1 and 725-2, and part of the dummywire 824. The moisture-resistant ring 714 includes the wall 821, thedummy wires 822-1 to 822-3, the walls 823-1 to 823-3, and part of thedummy wire 824. The dummy wire 824 is placed at the boundary between themoisture-resistant rings 712Le, 712Re, and 714, and themoisture-resistant ring 713 e, and is included as a component of eachmoisture-resistant ring.

Incidentally, the dummy wire 824 is described below, separated into aring portion 824A and lid portions 824B-1 and 824B-2 by auxiliary linesindicated by dotted lines of FIG. 66, as appropriate.

The dummy wires 822-1 to 822-3 have substantially the same rectangularring shape, and are formed, leaving a predetermined space from themoisture-resistant rings 712Le and 712Re, in each wiring layer in such amanner as to surround the periphery of the scribe area 42.

The wall 821 and the walls 823-1 to 823-3 have substantially the samerectangular ring shape, and are formed, leaving a predetermined spacefrom the moisture-resistant rings 712Le and 712Re, in such a manner asto surround the periphery of the scribe area 42.

The wall 821 is formed in the same step as the walls 723L and 723R, andconnects the substrate layer 751 and the dummy wire 822-1.

The walls 823-1 to 823-3 are formed in the same step as vias thatconnect adjacent wiring layers of the first to fourth wiring layers. Thewall 823-1 is a via that connects the dummy wires 822-1 and 822-2. Thewall 823-2 is a via that connects the dummy wires 822-2 and 822-3. Thewall 823-3 is a via that connects the dummy wires 822-3 and 824.

The ring portion 824A of the dummy wire 824 has the same shape as thedummy wire 722-1 of FIG. 43. Therefore, the dummy wire 824 has the shapeof the dummy wire 722-1 with the addition of the lid portions 824B-1 and824B-2.

The lid portion 824B-1 has a rectangular plate shape extending in thefront-and-back direction, and connects the front side and the back sideof the ring portion 824A. The left side surface of the lid portion824B-1 is at substantially the same position as the left side surface ofthe right side of the dummy wire 721L-3 in the left-and-right direction.The right side surface of the lid portion 824B-1 is at substantially thesame position as the right side surface of the left side of the dummywire 822-3 in the left-and-right direction.

Therefore, a barrier unit including the partial ring portion 824A andthe lid portion 824B-1 blocks an upper surface of an area between themoisture-resistant rings 712Le and 714. In other words, the barrier unitseparates the area between the moisture-resistant rings 712Le and 714and an area surrounded by the moisture-resistant ring 713 e.

The lid portion 824B-2 has a rectangular plate shape extending in thefront-and-back direction, and connects the front side and the back sideof the ring portion 824A. The left side surface of the lid portion824B-2 is at substantially the same position as the left side surface ofthe right side of the dummy wire 822-3 in the left-and-right direction.The right side surface of the lid portion 824B-2 is at substantially thesame position as the right side surface of the left side of the dummywire 721R-3 in the left-and-right direction.

Therefore, a barrier unit including the partial ring portion 824A andthe lid portion 824B-2 blocks an upper surface of an area between themoisture-resistant rings 712Re and 714. In other words, the barrier unitseparates the area between the moisture-resistant rings 712Re and 714and an area surrounded by the moisture-resistant ring 713 e.

As described above, the moisture-resistant rings 712Le, 712Re, 713 e,and 714 ensure the separation of non-moisture resistant areas 831 and amoisture-resistant area 832 as illustrated in FIGS. 67 and 68.Accordingly, moisture that has entered the non-moisture resistant area831 is prevented from entering the moisture-resistant area 832.Therefore, the moisture resistance of the moisture-resistant area 832 isretained, and the reliability of a solid state imaging device using thelogic substrate 701 improves.

Incidentally, in the fifth embodiment of the moisture-resistant ringwith the dual-layer structure, a moisture-resistant ring 715 is formedalso in the scribe area 42 that is actually cut between adjacent logicsubstrates 701 as illustrated in FIG. 69. The moisture-resistant ring715 includes a wall 825, dummy wires 826-1 to 826-4, and walls 827-1 to827-3.

The dummy wires 826-1 to 826-4 are respectively formed in the first tofourth wiring layers, and have substantially the same rectangular ringshape as the dummy wires 822-1 to 822-3 of the moisture-resistant ring714. The dummy wires 826-1 to 826-4 are formed in the wiring layers,leaving a predetermined space from the moisture-resistant ring 712Re ofthe left logic substrate 701 and the moisture-resistant ring 712Le ofthe right logic substrate 701, in such a manner as to surround theperiphery of the scribe area 42.

The wall 825 and the walls 826-1 to 826-3 have substantially the samerectangular ring shape as the wall 821 and the walls 823-1 to 823-3 ofthe moisture-resistant ring 714. The walls 825 and the walls 826-1 to826-3 are formed, leaving a predetermined space from themoisture-resistant ring 712Re of the left logic substrate 701 and themoisture-resistant ring 712Le of the right logic substrate 701, in sucha manner as to surround the periphery of the scribe area 42.

The wall 825 is formed in the same step as the walls 723L, 723R, and821, and connects the substrate layer 751 and the dummy wire 826-1.

The walls 827-1 to 827-3 are formed in the same step as vias thatconnect adjacent wiring layers of the first to fourth wiring layers. Thewall 827-1 is a via that connects the dummy wires 826-1 and 826-2. Thewall 827-2 is a via that connects the dummy wires 826-2 and 826-3. Thewall 827-3 is a via that connects the dummy wires 826-3 and 826-4.

The moisture-resistant ring 715 is then cut in the front-and-backdirection as indicated by a dotted line of FIG. 69 upon the manufactureof the solid state imaging device 1. However, the left side surface ofthe logic substrate 701 has a double structure of the moisture-resistantrings 715 and 712Le. The right side surface of the logic substrate 701has a double structure of the moisture-resistant rings 715 and 712Re.Therefore, even if the moisture-resistant ring 715 is cut, moistureresistance does not decrease.

Incidentally, split exposure is used to form the fourth wiring layerincluding the dummy wires 824 and 826-4. On the other hand, one-shotexposure is used to form the layers below the fourth wiring. In otherwords, one-shot exposure is used to form the layers excluding the dummywires 824 and 826-4 of the moisture-resistant rings 714 and 715.

Moreover, the moisture-resistant ring 714 is provided to enable areduction in the areas of the lid portions 824B-1 and 824B-2 of thedummy wire 824 as compared to the above-mentioned lid portion 741B ofthe dummy wire 741 of FIG. 46. Accordingly, manufacturing isfacilitated.

Furthermore, as compared to the above-mentioned technology disclosed inPatent Document 3, there is no need to provide a moisture-resistant filmdedicated to ensure moisture resistance. Accordingly, it is possible toreduce the manufacturing process and reduce the manufacturing cost.

Next, a modification of the above-mentioned moisture-resistant ring withthe double structure is described.

In the above description, the example is illustrated in which thebarrier unit is provided only below the substrate moisture-resistantring surrounding the periphery of the logic substrate. However, thebarrier unit may also be provided above the substrate moisture-resistantring.

FIGS. 70 and 71 schematically illustrate a cross-sectional view of theA-A part and a cross-sectional view of the B-B part of FIG. 41 of whenthe barrier unit is also provided above the substrate moisture-resistantring.

In this example, a circuit moisture-resistant ring 841L and a circuitmoisture-resistant ring 841R (not illustrated) are formed on thesubstrate layer 751. On the other hand, a circuit moisture-resistantring 842L and a circuit moisture-resistant ring 842R (not illustrated)are formed downward from the uppermost layer of the logic substrate 701.Moreover, a substrate moisture-resistant ring 843 is formed between thecircuit moisture-resistant rings 841L and 841R and the circuitmoisture-resistant rings 842L and 842R.

Then, a barrier unit that separates an area between the circuitmoisture-resistant rings 841L and 841R and an area surrounded by thesubstrate moisture-resistant ring 843 is formed by any of theabove-mentioned methods. Similarly, a barrier unit that separates anarea between the circuit moisture-resistant rings 842L and 842R and anarea surrounded by the substrate moisture-resistant ring 843 is formed.In other words, the barrier unit is also provided above in addition tobelow the substrate moisture-resistant ring 843.

Consequently, the separation of a non-moisture resistant area 851 and amoisture-resistant area 852 is ensured.

Incidentally, the barrier unit that blocks an entire opening portion ofan upper surface of the substrate moisture-resistant ring 843 may beformed without providing the circuit moisture-resistant rings 842L and842R.

Moreover, for example, it is also possible to reverse the stacking orderof the circuit moisture-resistant ring and the substratemoisture-resistant ring. For example, the substrate moisture-resistantring may be formed on the substrate layer 751 of the logic substrate 701and the circuit moisture-resistant ring may be formed on the substratemoisture-resistant ring.

Moreover, the moisture-resistant ring 712L and the moisture-resistantrings 712La to 712Le are not necessarily required to be formed in such amanner as to surround the entire periphery of the signal processingcircuit 711L, and may, for example, surround only part of the peripheryof the signal processing circuit 711L within a range that can ensuremoisture resistance. Similarly, the moisture-resistant ring 712R and themoisture-resistant tings 712Ra to 712Re are not necessarily required tobe formed in such a manner as to surround the entire periphery of thesignal processing circuit 711R, and may, for example, surround only partof the periphery of the signal processing circuit 711R within a rangethat can ensure moisture resistance.

Moreover, the moisture-resistant ring 713 and the moisture-resistantrings 713 a to 713 e are not necessarily required to be formed in such amanner as to surround the entire periphery of the logic substrate 701,and may, for example, surround only part of the periphery of the logicsubstrate 701 within the range that can ensure moisture resistance.

Furthermore, also if, for example, three or more signal processingcircuits are placed in the logic substrate, it is similarly required toform the circuit moisture-resistant ring surrounding the periphery orpart of the periphery of each signal processing circuit and thesubstrate moisture-resistant ring surrounding the periphery or part ofthe periphery of the logic substrate. It is then simply required to formthe above-mentioned barrier unit between adjacent circuitmoisture-resistant rings if needed.

Incidentally, the number of layers and material of the above-mentionedmoisture-resistant ring, and the material of the inter-layer insulatingfilm are mere examples, and can be changed if needed.

{5-2. Modification of the Imaging Process}

In the above description, the example is illustrated in which the signalprocessing circuits generate one sheet of image data divided into leftand right parts. However, the method for dividing image data can befreely changed in accordance with the number of the signal processingcircuits provided to the logic substrate and their layout. For example,image data may be divided into upper and lower parts or into n (n isthree or more).

Moreover, for example, each of a plurality of (for example, two) signalprocessing circuits may generate entire image data without dividingimage data, and generate image data to which pixel values of a pluralityof sets of the generated image data are added. Consequently, it ispossible to reduce random noise, absorb differences in thecharacteristics of the AD converters 81, and accordingly, improve imagequality.

In this case, the pixel values of the plurality of sets of image dataare assigned a weight to be added. For example, entire image data isgenerated by each of the two signal processing circuits, and added witha weight of 0.5. Accordingly, image data including average values ofpixel values of the two sheets of entire image data can be obtained.

Furthermore, for example, image data may be divided, and also aplurality of signal processing circuits may generate image data of thesame area to add the image data. For example, a left and a right signalprocessing circuit is provided redundantly. Two sets of image data ofthe left half of an object may be created, and two sets of image data ofthe right half may be generated. In addition, for example, image dataobtained by adding pixel values of the two sets of the image data of theleft half and image data obtained by adding pixel values of the two setsof the image data of the right half may be combined.

{5-3. Modification within the Scope of Application of the PresentTechnology}

In the above description, the example where the present technology isapplied to a solid state imaging device is illustrated. However, thepresent technology can also be applied to another stacked-structuresemiconductor device whose chip size is larger than the exposure fieldof the exposure apparatus.

<6. Electronic Apparatus>

A solid state imaging device to which the present technology is appliedcan be used as an imaging unit (image capture unit) in an imagingapparatus such as a digital still camera or a video camera, a mobileterminal apparatus having an imaging function such as a mobile phone,and a general electronic apparatus such as a copier using a solid stateimaging device in an image reading unit. Incidentally, the abovemodule-like form mounted on an electronic apparatus, that is, a cameramodule may be used as an imaging apparatus.

{6-1. Imaging Apparatus}

FIG. 72 is a block diagram illustrating a configuration example of animaging apparatus (camera apparatus) 901 being an example of anelectronic apparatus to which the present technology is applied.

As illustrated in FIG. 72, the imaging apparatus 901 includes an opticalsystem including a lens group 911, an imaging device 912, a DSP circuit913 being a camera signal processing unit, a frame memory 914, a displayapparatus 915, a recording apparatus 916, an operating system 917, and apower supply system 918. In addition, a configuration is adopted inwhich the DSP circuit 913, the frame memory 914, the display apparatus915, the recording apparatus 916, the operating system 917, and thepower supply system 918 are connected to one another via a bus line 919.

The lens group 911 captures incident light (image light) from an objectand forms an image on an imaging surface of the imaging device 912. Theimaging device 912 converts the light quantity of the incident lightwhose image has been formed on the imaging surface by the lens group 911into an electrical signal, pixel by pixel, and outputs it as a pixelsignal.

The display apparatus 915 includes a panel display apparatus such as aliquid crystal display apparatus or an organic electro luminescence (EL)display apparatus, and displays a moving image or still image capturedby the imaging device 912. The recording apparatus 916 records themoving or still image captured by the imaging device 912 in a recordingmedium such as a memory card, a video tape, or a digital versatile disk(DVD).

The operating system 917 issues operation commands on various functionsof the imaging apparatus 901 under the user's operation. The powersupply system 918 supplies various powers being operating powers of theDSP circuit 913, the frame memory 914, the display apparatus 915, therecording apparatus 916, and the operating system 917 to these supplytargets as appropriate.

Such an imaging apparatus 901 is applied to a video camera and a digitalstill camera, and is further applied to a camera module designed formobile equipment such as a smartphone and a mobile phone. In addition,in the imaging apparatus 901, the solid state imaging devices accordingto the above-mentioned embodiments can be used as the imaging device912. Consequently, the cost of the imaging apparatus 901 can be reduced.

Incidentally, embodiments of the present technology are not limited tothe above-mentioned embodiments. Various modifications can be madewithin a range that does not depart from the gist of the presenttechnology.

Moreover, for example, the present technology can also take thefollowing configurations.

(1)

A solid state imaging device including:

a first substrate including a pixel circuit having a pixel array unit;and

a second substrate including a first and a second signal processingcircuit arranged side by side across a scribe area,

wherein the first substrate and the second substrate are stacked, and

the second substrate includes

-   -   a first moisture-resistant ring surrounding at least part of a        periphery of the first signal processing circuit,    -   a second moisture-resistant ring surrounding at least part of a        periphery of the second signal processing circuit,    -   a third moisture-resistant ring surrounding at least part of a        periphery of the second substrate in a layer different from the        first and second moisture-resistant rings, and    -   a barrier unit separating a first area between the first and        second moisture-resistant rings and a second area, at least part        of a periphery of which is surrounded by the third        moisture-resistant ring, and having moisture resistance.

(2)

The solid state imaging device according to (1), wherein the barrierunit includes a dummy wire being a wire that is not used to transmit asignal.

(3)

The solid state imaging device according to (2), wherein the barrierunit includes a plurality of the dummy wires formed in a plurality ofwiring layers, and a via connecting the dummy wires in different wiringlayers.

(4)

The solid state imaging device according to (3), wherein the dummy wiresin a first wiring layer and the dummy wires in a second wiring layeradjacent to the first wiring layer are alternately placed in a firstdirection in which the scribe area extends, or a second directionperpendicular to the first direction in at least part of the barrierunit.

(5)

The solid state imaging device according to (4), wherein a wire thatconnects the first and second signal processing circuits is formed inthe first or second wiring layer that is closer to the thirdmoisture-resistant ring.

(6)

The solid state imaging device according to (1),

wherein the second substrate further includes a fourthmoisture-resistant ring formed, leaving a predetermined space from thefirst and second moisture-resistant rings, in such a manner as tosurround at least part of a periphery of the scribe area, and

the barrier unit separates a third area between the first and fourthmoisture-resistant rings and the second area, and a fourth area betweenthe second and fourth moisture-resistant rings and the second area,between the first area and the second area.

(7)

The solid state imaging device according to any of (1) to (6),

wherein at least part of a layer including the first and secondmoisture-resistant rings is formed by one-shot exposure, and

layers including the third moisture-resistant ring and the barrier unitare formed by split exposure.

(8)

The solid state imaging device according to any of (1) to (7), whereinan inter-layer insulating film between the layer including the barrierunit and an adjacent layer thereof includes a low-K film.

(9)

The solid state imaging device according to any of (1) to (8), wherein awire that connects the first and second signal processing circuits isformed in the layer including the third moisture-resistant ring.

(10)

The solid state imaging device according to any of (1) to (9),

wherein the pixel circuit is formed by split exposure, and

at least part of the layers of the signal processing circuits are formedby one-shot exposure.

(11)

An electronic apparatus including a solid state imaging device including

a first substrate including a pixel circuit having a pixel array unit,and

a second substrate including a first and a second signal processingcircuit arranged side by side across a scribe area,

wherein the first substrate and the second substrate are stacked, and

the second substrate includes

-   -   a first moisture-resistant ring surrounding at least part of a        periphery of the first signal processing circuit,    -   a second moisture-resistant ring surrounding at least part of a        periphery of the second signal processing circuit,    -   a third moisture-resistant ring surrounding at least part of a        periphery of the second substrate in a layer different from the        first and second moisture-resistant rings, and    -   a barrier unit separating a first area between the first and        second moisture-resistant rings and a second area, at least part        of a periphery of which is surrounded by the third        moisture-resistant ring, and having moisture resistance.

REFERENCE SIGNS LIST

-   1 Solid state imaging device-   11 Pixel substrate-   12 Logic substrate-   21 Pixel circuit-   22 Scribe area-   31 Pixel array unit-   32 Unit pixel-   41L, 41R Signal processing circuit-   42 Scribe area-   701 Logic substrate-   711L, 711R Signal processing circuit-   712L, 712La to 712Le, 712R, 712Ra to 712Re, 713, 713 a to 713 e,-   714, 715 Moisture-resistant ring-   721L-1 to 721R-3, 722-1 to 722-3 Dummy wire-   723L, 723R, 724L-1 to 724R-3, 725-1, 725-2 Wall-   741 Dummy wire-   751 Substrate layer-   752 Non-moisture resistant area-   753 Moisture-resistant area-   761 Dummy wire-   762 Wall-   763 Dummy wire-   771 Non-moisture resistant area-   772 Moisture-resistant area-   781 Dummy wire-   782, 783-1 to 783-n Wall-   784, 785-1 to 785-n Dummy wire-   791 Non-moisture resistant area-   792 Moisture-resistant area-   801-1, 801-2 Wire-   821 Wall-   822-1 to 822-3 Dummy wire-   823-1 to 823-3 Wall-   824 Dummy wire-   825 Wall-   826-1 to 826-4 Dummy wire-   827-1 to 827-4 Wall-   831 Non-moisture resistant area-   832 Moisture-resistant area-   841L, 841R, 842L, 842R, 843 Moisture-resistant ring-   851 Non-moisture resistant area-   852 Moisture-resistant area-   901 Imaging apparatus-   912 Imaging device

What is claimed is:
 1. A solid state imaging device comprising: a firstsubstrate including a pixel circuit having a pixel array unit; and asecond substrate including a first and a second signal processingcircuit arranged side by side across a scribe area, wherein the firstsubstrate and the second substrate are stacked, and the second substrateincludes a first moisture-resistant ring surrounding at least part of aperiphery of the first signal processing circuit, a secondmoisture-resistant ring surrounding at least part of a periphery of thesecond signal processing circuit, a third moisture-resistant ringsurrounding at least part of a periphery of the second substrate in alayer different from the first and second moisture-resistant rings, anda barrier unit separating a first area between the first and secondmoisture-resistant rings and a second area, at least part of a peripheryof which is surrounded by the third moisture-resistant ring, and havingmoisture resistance.
 2. The solid state imaging device according toclaim 1, wherein the barrier unit includes a dummy wire being a wirethat is not used to transmit a signal.
 3. The solid state imaging deviceaccording to claim 2, wherein the barrier unit includes a plurality ofthe dummy wires formed in a plurality of wiring layers, and a viaconnecting the dummy wires in different wiring layers.
 4. The solidstate imaging device according to claim 3, wherein the dummy wires in afirst wiring layer and the dummy wires in a second wiring layer adjacentto the first wiring layer are alternately placed in a first direction inwhich the scribe area extends, or a second direction perpendicular tothe first direction in at least part of the barrier unit.
 5. The solidstate imaging device according to claim 4, wherein a wire that connectsthe first and second signal processing circuits is formed in the firstor second wiring layer that is closer to the third moisture-resistantring.
 6. The solid state imaging device according to claim 1, whereinthe second substrate further includes a fourth moisture-resistant ringformed, leaving a predetermined space from the first and secondmoisture-resistant rings, in such a manner as to surround at least partof a periphery of the scribe area, and the barrier unit separates athird area between the first and fourth moisture-resistant rings and thesecond area, and a fourth area between the second and fourthmoisture-resistant rings and the second area.
 7. The solid state imagingdevice according to claim 1, wherein at least part of a layer includingthe first and second moisture-resistant rings is formed by one-shotexposure, and layers including the third moisture-resistant ring and thebarrier unit are formed by split exposure.
 8. The solid state imagingdevice according to claim 1, wherein an inter-layer insulating filmbetween the layer including the barrier unit and an adjacent layerthereof comprises a low-K film.
 9. The solid state imaging deviceaccording to claim 1, wherein a wire that connects the first and secondsignal processing circuits is formed in the layer including the thirdmoisture-resistant ring.
 10. The solid state imaging device according toclaim 1, wherein the pixel circuit is formed by split exposure, and atleast part of the layers of the signal processing circuits are formed byone-shot exposure.
 11. An electronic apparatus comprising a solid stateimaging device including a first substrate including a pixel circuithaving a pixel array unit, and a second substrate including a first anda second signal processing circuit arranged side by side across a scribearea, wherein the first substrate and the second substrate are stacked,and the second substrate includes a first moisture-resistant ringsurrounding at least part of a periphery of the first signal processingcircuit, a second moisture-resistant ring surrounding at least part of aperiphery of the second signal processing circuit, a thirdmoisture-resistant ring surrounding at least part of a periphery of thesecond substrate in a layer different from the first and secondmoisture-resistant rings, and a barrier unit separating a first areabetween the first and second moisture-resistant rings and a second area,at least part of a periphery of which is surrounded by the thirdmoisture-resistant ring, and having moisture resistance.